|
const std = @import("std.zig"); const io = std.io; const os = std.os; const math = std.math; const mem = std.mem; const assert = std.debug.assert; const File = std.fs.File; const native_endian = @import("builtin").target.cpu.arch.endian(); |
AT_NULLSymbol is global |
pub const AT_NULL = 0; |
AT_IGNOREBeginning of reserved entries |
pub const AT_IGNORE = 1; |
AT_EXECFDSymbol is to be eliminated |
pub const AT_EXECFD = 2; |
AT_PHDRVersion definition of the file itself |
pub const AT_PHDR = 3; |
AT_PHENTWeak version identifier |
pub const AT_PHENT = 4; |
AT_PHNUMProgram header table entry unused |
pub const AT_PHNUM = 5; |
AT_PAGESZLoadable program segment |
pub const AT_PAGESZ = 6; |
AT_BASEDynamic linking information |
pub const AT_BASE = 7; |
AT_FLAGSProgram interpreter |
pub const AT_FLAGS = 8; |
AT_ENTRYAuxiliary information |
pub const AT_ENTRY = 9; |
AT_NOTELFReserved |
pub const AT_NOTELF = 10; |
AT_UIDEntry for header table itself |
pub const AT_UID = 11; |
AT_EUIDThread-local storage segment |
pub const AT_EUID = 12; |
AT_GIDNumber of defined types |
pub const AT_GID = 13; |
AT_EGIDStart of OS-specific |
pub const AT_EGID = 14; |
AT_CLKTCKGCC .eh_frame_hdr segment |
pub const AT_CLKTCK = 17; |
AT_PLATFORMIndicates stack executability |
pub const AT_PLATFORM = 15; |
AT_HWCAPRead-only after relocation |
pub const AT_HWCAP = 16; |
AT_FPUCWSun specific segment |
pub const AT_FPUCW = 18; |
AT_DCACHEBSIZEStack segment |
pub const AT_DCACHEBSIZE = 19; |
AT_ICACHEBSIZEEnd of OS-specific |
pub const AT_ICACHEBSIZE = 20; |
AT_UCACHEBSIZEStart of processor-specific |
pub const AT_UCACHEBSIZE = 21; |
AT_IGNOREPPCEnd of processor-specific |
pub const AT_IGNOREPPC = 22; |
AT_SECURESection header table entry unused |
pub const AT_SECURE = 23; |
AT_BASE_PLATFORMProgram data |
pub const AT_BASE_PLATFORM = 24; |
AT_RANDOMSymbol table |
pub const AT_RANDOM = 25; |
AT_HWCAP2String table |
pub const AT_HWCAP2 = 26; |
AT_EXECFNRelocation entries with addends |
pub const AT_EXECFN = 31; |
AT_SYSINFOSymbol hash table |
pub const AT_SYSINFO = 32; |
AT_SYSINFO_EHDRDynamic linking information |
pub const AT_SYSINFO_EHDR = 33; |
AT_L1I_CACHESHAPENotes |
pub const AT_L1I_CACHESHAPE = 34; |
AT_L1D_CACHESHAPEProgram space with no data (bss) |
pub const AT_L1D_CACHESHAPE = 35; |
AT_L2_CACHESHAPERelocation entries, no addends |
pub const AT_L2_CACHESHAPE = 36; |
AT_L3_CACHESHAPEReserved |
pub const AT_L3_CACHESHAPE = 37; |
AT_L1I_CACHESIZEDynamic linker symbol table |
pub const AT_L1I_CACHESIZE = 40; |
AT_L1I_CACHEGEOMETRYArray of constructors |
pub const AT_L1I_CACHEGEOMETRY = 41; |
AT_L1D_CACHESIZEArray of destructors |
pub const AT_L1D_CACHESIZE = 42; |
AT_L1D_CACHEGEOMETRYArray of pre-constructors |
pub const AT_L1D_CACHEGEOMETRY = 43; |
AT_L2_CACHESIZESection group |
pub const AT_L2_CACHESIZE = 44; |
AT_L2_CACHEGEOMETRYExtended section indices |
pub const AT_L2_CACHEGEOMETRY = 45; |
AT_L3_CACHESIZEStart of OS-specific |
pub const AT_L3_CACHESIZE = 46; |
AT_L3_CACHEGEOMETRYLLVM address-significance table |
pub const AT_L3_CACHEGEOMETRY = 47; |
DT_NULLGNU hash table |
pub const DT_NULL = 0; |
DT_NEEDEDGNU version definition table |
pub const DT_NEEDED = 1; |
DT_PLTRELSZGNU needed versions table |
pub const DT_PLTRELSZ = 2; |
DT_PLTGOTGNU symbol version table |
pub const DT_PLTGOT = 3; |
DT_HASHEnd of OS-specific |
pub const DT_HASH = 4; |
DT_STRTABStart of processor-specific |
pub const DT_STRTAB = 5; |
DT_SYMTABUnwind information |
pub const DT_SYMTAB = 6; |
DT_RELAEnd of processor-specific |
pub const DT_RELA = 7; |
DT_RELASZStart of application-specific |
pub const DT_RELASZ = 8; |
DT_RELAENTEnd of application-specific |
pub const DT_RELAENT = 9; |
DT_STRSZLocal symbol |
pub const DT_STRSZ = 10; |
DT_SYMENTGlobal symbol |
pub const DT_SYMENT = 11; |
DT_INITWeak symbol |
pub const DT_INIT = 12; |
DT_FININumber of defined types |
pub const DT_FINI = 13; |
DT_SONAMEStart of OS-specific |
pub const DT_SONAME = 14; |
DT_RPATHUnique symbol |
pub const DT_RPATH = 15; |
DT_SYMBOLICEnd of OS-specific |
pub const DT_SYMBOLIC = 16; |
DT_RELStart of processor-specific |
pub const DT_REL = 17; |
DT_RELSZEnd of processor-specific |
pub const DT_RELSZ = 18; |
DT_RELENTSymbol type is unspecified |
pub const DT_RELENT = 19; |
DT_PLTRELSymbol is a data object |
pub const DT_PLTREL = 20; |
DT_DEBUGSymbol is a code object |
pub const DT_DEBUG = 21; |
DT_TEXTRELSymbol associated with a section |
pub const DT_TEXTREL = 22; |
DT_JMPRELSymbol's name is file name |
pub const DT_JMPREL = 23; |
DT_BIND_NOWSymbol is a common data object |
pub const DT_BIND_NOW = 24; |
DT_INIT_ARRAYSymbol is thread-local data object |
pub const DT_INIT_ARRAY = 25; |
DT_FINI_ARRAYNumber of defined types |
pub const DT_FINI_ARRAY = 26; |
DT_INIT_ARRAYSZStart of OS-specific |
pub const DT_INIT_ARRAYSZ = 27; |
DT_FINI_ARRAYSZSymbol is indirect code object |
pub const DT_FINI_ARRAYSZ = 28; |
DT_RUNPATHEnd of OS-specific |
pub const DT_RUNPATH = 29; |
DT_FLAGSStart of processor-specific |
pub const DT_FLAGS = 30; |
DT_ENCODINGEnd of processor-specific |
pub const DT_ENCODING = 32; |
DT_PREINIT_ARRAYFile types |
pub const DT_PREINIT_ARRAY = 32; |
DT_PREINIT_ARRAYSZNo file type |
pub const DT_PREINIT_ARRAYSZ = 33; |
DT_SYMTAB_SHNDXRelocatable file |
pub const DT_SYMTAB_SHNDX = 34; |
DT_NUMExecutable file |
pub const DT_NUM = 35; |
DT_LOOSShared object file |
pub const DT_LOOS = 0x6000000d; |
DT_HIOSCore file |
pub const DT_HIOS = 0x6ffff000; |
DT_LOPROCBeginning of processor-specific codes |
pub const DT_LOPROC = 0x70000000; |
DT_HIPROCProcessor-specific |
pub const DT_HIPROC = 0x7fffffff; |
DT_PROCNUMAll integers are native endian. |
pub const DT_PROCNUM = DT_MIPS_NUM; |
DT_VALRNGLOMachine architectures. See current registered ELF machine architectures at: http://www.sco.com/developers/gabi/latest/ch4.eheader.html |
pub const DT_VALRNGLO = 0x6ffffd00; |
DT_GNU_PRELINKEDNo machine |
pub const DT_GNU_PRELINKED = 0x6ffffdf5; |
DT_GNU_CONFLICTSZAT&T WE 32100 |
pub const DT_GNU_CONFLICTSZ = 0x6ffffdf6; |
DT_GNU_LIBLISTSZSPARC |
pub const DT_GNU_LIBLISTSZ = 0x6ffffdf7; |
DT_CHECKSUMIntel 386 |
pub const DT_CHECKSUM = 0x6ffffdf8; |
DT_PLTPADSZMotorola 68000 |
pub const DT_PLTPADSZ = 0x6ffffdf9; |
DT_MOVEENTMotorola 88000 |
pub const DT_MOVEENT = 0x6ffffdfa; |
DT_MOVESZIntel MCU |
pub const DT_MOVESZ = 0x6ffffdfb; |
DT_FEATURE_1Intel 80860 |
pub const DT_FEATURE_1 = 0x6ffffdfc; |
DT_POSFLAG_1MIPS R3000 |
pub const DT_POSFLAG_1 = 0x6ffffdfd; |
DT_SYMINSZIBM System/370 |
pub const DT_SYMINSZ = 0x6ffffdfe; |
DT_SYMINENTMIPS RS3000 Little-endian |
pub const DT_SYMINENT = 0x6ffffdff; |
DT_VALRNGHISPU Mark II |
pub const DT_VALRNGHI = 0x6ffffdff; |
DT_VALNUMHewlett-Packard PA-RISC |
pub const DT_VALNUM = 12; |
DT_ADDRRNGLOFujitsu VPP500 |
pub const DT_ADDRRNGLO = 0x6ffffe00; |
DT_GNU_HASHEnhanced instruction set SPARC |
pub const DT_GNU_HASH = 0x6ffffef5; |
DT_TLSDESC_PLTIntel 80960 |
pub const DT_TLSDESC_PLT = 0x6ffffef6; |
DT_TLSDESC_GOTPowerPC |
pub const DT_TLSDESC_GOT = 0x6ffffef7; |
DT_GNU_CONFLICTPowerPC64 |
pub const DT_GNU_CONFLICT = 0x6ffffef8; |
DT_GNU_LIBLISTIBM System/390 |
pub const DT_GNU_LIBLIST = 0x6ffffef9; |
DT_CONFIGIBM SPU/SPC |
pub const DT_CONFIG = 0x6ffffefa; |
DT_DEPAUDITNEC V800 |
pub const DT_DEPAUDIT = 0x6ffffefb; |
DT_AUDITFujitsu FR20 |
pub const DT_AUDIT = 0x6ffffefc; |
DT_PLTPADTRW RH-32 |
pub const DT_PLTPAD = 0x6ffffefd; |
DT_MOVETABMotorola RCE |
pub const DT_MOVETAB = 0x6ffffefe; |
DT_SYMINFOARM |
pub const DT_SYMINFO = 0x6ffffeff; |
DT_ADDRRNGHIDEC Alpha |
pub const DT_ADDRRNGHI = 0x6ffffeff; |
DT_ADDRNUMHitachi SH |
pub const DT_ADDRNUM = 11; |
DT_VERSYMSPARC V9 |
pub const DT_VERSYM = 0x6ffffff0; |
DT_RELACOUNTSiemens TriCore |
pub const DT_RELACOUNT = 0x6ffffff9; |
DT_RELCOUNTArgonaut RISC Core |
pub const DT_RELCOUNT = 0x6ffffffa; |
DT_FLAGS_1Hitachi H8/300 |
pub const DT_FLAGS_1 = 0x6ffffffb; |
DT_VERDEFHitachi H8/300H |
pub const DT_VERDEF = 0x6ffffffc; |
DT_VERDEFNUMHitachi H8S |
pub const DT_VERDEFNUM = 0x6ffffffd; |
DT_VERNEEDHitachi H8/500 |
pub const DT_VERNEED = 0x6ffffffe; |
DT_VERNEEDNUMIntel IA-64 processor architecture |
pub const DT_VERNEEDNUM = 0x6fffffff; |
DT_VERSIONTAGNUMStanford MIPS-X |
pub const DT_VERSIONTAGNUM = 16; |
DT_AUXILIARYMotorola ColdFire |
pub const DT_AUXILIARY = 0x7ffffffd; |
DT_FILTERMotorola M68HC12 |
pub const DT_FILTER = 0x7fffffff; |
DT_EXTRANUMFujitsu MMA Multimedia Accelerator |
pub const DT_EXTRANUM = 3; |
DT_SPARC_REGISTERSiemens PCP |
pub const DT_SPARC_REGISTER = 0x70000001; |
DT_SPARC_NUMSony nCPU embedded RISC processor |
pub const DT_SPARC_NUM = 2; |
DT_MIPS_RLD_VERSIONDenso NDR1 microprocessor |
pub const DT_MIPS_RLD_VERSION = 0x70000001; |
DT_MIPS_TIME_STAMPMotorola Star*Core processor |
pub const DT_MIPS_TIME_STAMP = 0x70000002; |
DT_MIPS_ICHECKSUMToyota ME16 processor |
pub const DT_MIPS_ICHECKSUM = 0x70000003; |
DT_MIPS_IVERSIONSTMicroelectronics ST100 processor |
pub const DT_MIPS_IVERSION = 0x70000004; |
DT_MIPS_FLAGSAdvanced Logic Corp. TinyJ embedded processor family |
pub const DT_MIPS_FLAGS = 0x70000005; |
DT_MIPS_BASE_ADDRESSAMD x86-64 architecture |
pub const DT_MIPS_BASE_ADDRESS = 0x70000006; |
DT_MIPS_MSYMSony DSP Processor |
pub const DT_MIPS_MSYM = 0x70000007; |
DT_MIPS_CONFLICTDigital Equipment Corp. PDP-10 |
pub const DT_MIPS_CONFLICT = 0x70000008; |
DT_MIPS_LIBLISTDigital Equipment Corp. PDP-11 |
pub const DT_MIPS_LIBLIST = 0x70000009; |
DT_MIPS_LOCAL_GOTNOSiemens FX66 microcontroller |
pub const DT_MIPS_LOCAL_GOTNO = 0x7000000a; |
DT_MIPS_CONFLICTNOSTMicroelectronics ST9+ 8/16 bit microcontroller |
pub const DT_MIPS_CONFLICTNO = 0x7000000b; |
DT_MIPS_LIBLISTNOSTMicroelectronics ST7 8-bit microcontroller |
pub const DT_MIPS_LIBLISTNO = 0x70000010; |
DT_MIPS_SYMTABNOMotorola MC68HC16 Microcontroller |
pub const DT_MIPS_SYMTABNO = 0x70000011; |
DT_MIPS_UNREFEXTNOMotorola MC68HC11 Microcontroller |
pub const DT_MIPS_UNREFEXTNO = 0x70000012; |
DT_MIPS_GOTSYMMotorola MC68HC08 Microcontroller |
pub const DT_MIPS_GOTSYM = 0x70000013; |
DT_MIPS_HIPAGENOMotorola MC68HC05 Microcontroller |
pub const DT_MIPS_HIPAGENO = 0x70000014; |
DT_MIPS_RLD_MAPSilicon Graphics SVx |
pub const DT_MIPS_RLD_MAP = 0x70000016; |
DT_MIPS_DELTA_CLASSSTMicroelectronics ST19 8-bit microcontroller |
pub const DT_MIPS_DELTA_CLASS = 0x70000017; |
DT_MIPS_DELTA_CLASS_NODigital VAX |
pub const DT_MIPS_DELTA_CLASS_NO = 0x70000018; |
DT_MIPS_DELTA_INSTANCEAxis Communications 32-bit embedded processor |
pub const DT_MIPS_DELTA_INSTANCE = 0x70000019; |
DT_MIPS_DELTA_INSTANCE_NOInfineon Technologies 32-bit embedded processor |
pub const DT_MIPS_DELTA_INSTANCE_NO = 0x7000001a; |
DT_MIPS_DELTA_RELOCElement 14 64-bit DSP Processor |
pub const DT_MIPS_DELTA_RELOC = 0x7000001b; |
DT_MIPS_DELTA_RELOC_NOLSI Logic 16-bit DSP Processor |
pub const DT_MIPS_DELTA_RELOC_NO = 0x7000001c; |
DT_MIPS_DELTA_SYMDonald Knuth's educational 64-bit processor |
pub const DT_MIPS_DELTA_SYM = 0x7000001d; |
DT_MIPS_DELTA_SYM_NOHarvard University machine-independent object files |
pub const DT_MIPS_DELTA_SYM_NO = 0x7000001e; |
DT_MIPS_DELTA_CLASSSYMSiTera Prism |
pub const DT_MIPS_DELTA_CLASSSYM = 0x70000020; |
DT_MIPS_DELTA_CLASSSYM_NOAtmel AVR 8-bit microcontroller |
pub const DT_MIPS_DELTA_CLASSSYM_NO = 0x70000021; |
DT_MIPS_CXX_FLAGSFujitsu FR30 |
pub const DT_MIPS_CXX_FLAGS = 0x70000022; |
DT_MIPS_PIXIE_INITMitsubishi D10V |
pub const DT_MIPS_PIXIE_INIT = 0x70000023; |
DT_MIPS_SYMBOL_LIBMitsubishi D30V |
pub const DT_MIPS_SYMBOL_LIB = 0x70000024; |
DT_MIPS_LOCALPAGE_GOTIDXNEC v850 |
pub const DT_MIPS_LOCALPAGE_GOTIDX = 0x70000025; |
DT_MIPS_LOCAL_GOTIDXMitsubishi M32R |
pub const DT_MIPS_LOCAL_GOTIDX = 0x70000026; |
DT_MIPS_HIDDEN_GOTIDXMatsushita MN10300 |
pub const DT_MIPS_HIDDEN_GOTIDX = 0x70000027; |
DT_MIPS_PROTECTED_GOTIDXMatsushita MN10200 |
pub const DT_MIPS_PROTECTED_GOTIDX = 0x70000028; |
DT_MIPS_OPTIONSpicoJava |
pub const DT_MIPS_OPTIONS = 0x70000029; |
DT_MIPS_INTERFACEOpenRISC 32-bit embedded processor |
pub const DT_MIPS_INTERFACE = 0x7000002a; |
DT_MIPS_DYNSTR_ALIGNARC International ARCompact processor (old spelling/synonym: EM_ARC_A5) |
pub const DT_MIPS_DYNSTR_ALIGN = 0x7000002b; |
DT_MIPS_INTERFACE_SIZETensilica Xtensa Architecture |
pub const DT_MIPS_INTERFACE_SIZE = 0x7000002c; |
DT_MIPS_RLD_TEXT_RESOLVE_ADDRAlphamosaic VideoCore processor |
pub const DT_MIPS_RLD_TEXT_RESOLVE_ADDR = 0x7000002d; |
DT_MIPS_PERF_SUFFIXThompson Multimedia General Purpose Processor |
pub const DT_MIPS_PERF_SUFFIX = 0x7000002e; |
DT_MIPS_COMPACT_SIZENational Semiconductor 32000 series |
pub const DT_MIPS_COMPACT_SIZE = 0x7000002f; |
DT_MIPS_GP_VALUETenor Network TPC processor |
pub const DT_MIPS_GP_VALUE = 0x70000030; |
DT_MIPS_AUX_DYNAMICTrebia SNP 1000 processor |
pub const DT_MIPS_AUX_DYNAMIC = 0x70000031; |
DT_MIPS_PLTGOTSTMicroelectronics (www.st.com) ST200 |
pub const DT_MIPS_PLTGOT = 0x70000032; |
DT_MIPS_RWPLTUbicom IP2xxx microcontroller family |
pub const DT_MIPS_RWPLT = 0x70000034; |
DT_MIPS_RLD_MAP_RELMAX Processor |
pub const DT_MIPS_RLD_MAP_REL = 0x70000035; |
DT_MIPS_NUMNational Semiconductor CompactRISC microprocessor |
pub const DT_MIPS_NUM = 0x36; |
DT_ALPHA_PLTROFujitsu F2MC16 |
pub const DT_ALPHA_PLTRO = (DT_LOPROC + 0); |
DT_ALPHA_NUMTexas Instruments embedded microcontroller msp430 |
pub const DT_ALPHA_NUM = 1; |
DT_PPC_GOTAnalog Devices Blackfin (DSP) processor |
pub const DT_PPC_GOT = (DT_LOPROC + 0); |
DT_PPC_OPTS1C33 Family of Seiko Epson processors |
pub const DT_PPC_OPT = (DT_LOPROC + 1); |
DT_PPC_NUMSharp embedded microprocessor |
pub const DT_PPC_NUM = 2; |
DT_PPC64_GLINKArca RISC Microprocessor |
pub const DT_PPC64_GLINK = (DT_LOPROC + 0); |
DT_PPC64_OPDMicroprocessor series from PKU-Unity Ltd. and MPRC of Peking University |
pub const DT_PPC64_OPD = (DT_LOPROC + 1); |
DT_PPC64_OPDSZeXcess: 16/32/64-bit configurable embedded CPU |
pub const DT_PPC64_OPDSZ = (DT_LOPROC + 2); |
DT_PPC64_OPTIcera Semiconductor Inc. Deep Execution Processor |
pub const DT_PPC64_OPT = (DT_LOPROC + 3); |
DT_PPC64_NUMAltera Nios II soft-core processor |
pub const DT_PPC64_NUM = 4; |
DT_IA_64_PLT_RESERVENational Semiconductor CompactRISC CRX |
pub const DT_IA_64_PLT_RESERVE = (DT_LOPROC + 0); |
DT_IA_64_NUMMotorola XGATE embedded processor |
pub const DT_IA_64_NUM = 1; |
DT_NIOS2_GPInfineon C16x/XC16x processor |
pub const DT_NIOS2_GP = 0x70000002; |
DF_ORIGINRenesas M16C series microprocessors |
pub const DF_ORIGIN = 0x00000001; |
DF_SYMBOLICMicrochip Technology dsPIC30F Digital Signal Controller |
pub const DF_SYMBOLIC = 0x00000002; |
DF_TEXTRELFreescale Communication Engine RISC core |
pub const DF_TEXTREL = 0x00000004; |
DF_BIND_NOWRenesas M32C series microprocessors |
pub const DF_BIND_NOW = 0x00000008; |
DF_STATIC_TLSAltium TSK3000 core |
pub const DF_STATIC_TLS = 0x00000010; |
DF_1_NOWFreescale RS08 embedded processor |
pub const DF_1_NOW = 0x00000001; |
DF_1_GLOBALAnalog Devices SHARC family of 32-bit DSP processors |
pub const DF_1_GLOBAL = 0x00000002; |
DF_1_GROUPCyan Technology eCOG2 microprocessor |
pub const DF_1_GROUP = 0x00000004; |
DF_1_NODELETESunplus S+core7 RISC processor |
pub const DF_1_NODELETE = 0x00000008; |
DF_1_LOADFLTRNew Japan Radio (NJR) 24-bit DSP Processor |
pub const DF_1_LOADFLTR = 0x00000010; |
DF_1_INITFIRSTBroadcom VideoCore III processor |
pub const DF_1_INITFIRST = 0x00000020; |
DF_1_NOOPENRISC processor for Lattice FPGA architecture |
pub const DF_1_NOOPEN = 0x00000040; |
DF_1_ORIGINSeiko Epson C17 family |
pub const DF_1_ORIGIN = 0x00000080; |
DF_1_DIRECTThe Texas Instruments TMS320C6000 DSP family |
pub const DF_1_DIRECT = 0x00000100; |
DF_1_TRANSThe Texas Instruments TMS320C2000 DSP family |
pub const DF_1_TRANS = 0x00000200; |
DF_1_INTERPOSEThe Texas Instruments TMS320C55x DSP family |
pub const DF_1_INTERPOSE = 0x00000400; |
DF_1_NODEFLIBSTMicroelectronics 64bit VLIW Data Signal Processor |
pub const DF_1_NODEFLIB = 0x00000800; |
DF_1_NODUMPCypress M8C microprocessor |
pub const DF_1_NODUMP = 0x00001000; |
DF_1_CONFALTRenesas R32C series microprocessors |
pub const DF_1_CONFALT = 0x00002000; |
DF_1_ENDFILTEENXP Semiconductors TriMedia architecture family |
pub const DF_1_ENDFILTEE = 0x00004000; |
DF_1_DISPRELDNEQualcomm Hexagon processor |
pub const DF_1_DISPRELDNE = 0x00008000; |
DF_1_DISPRELPNDIntel 8051 and variants |
pub const DF_1_DISPRELPND = 0x00010000; |
DF_1_NODIRECTSTMicroelectronics STxP7x family of configurable and extensible RISC processors |
pub const DF_1_NODIRECT = 0x00020000; |
DF_1_IGNMULDEFAndes Technology compact code size embedded RISC processor family |
pub const DF_1_IGNMULDEF = 0x00040000; |
DF_1_NOKSYMSCyan Technology eCOG1X family |
pub const DF_1_NOKSYMS = 0x00080000; |
DF_1_NOHDRDallas Semiconductor MAXQ30 Core Micro-controllers |
pub const DF_1_NOHDR = 0x00100000; |
DF_1_EDITEDNew Japan Radio (NJR) 16-bit DSP Processor |
pub const DF_1_EDITED = 0x00200000; |
DF_1_NORELOCM2000 Reconfigurable RISC Microprocessor |
pub const DF_1_NORELOC = 0x00400000; |
DF_1_SYMINTPOSECray Inc. NV2 vector architecture |
pub const DF_1_SYMINTPOSE = 0x00800000; |
DF_1_GLOBAUDITRenesas RX family |
pub const DF_1_GLOBAUDIT = 0x01000000; |
DF_1_SINGLETONImagination Technologies META processor architecture |
pub const DF_1_SINGLETON = 0x02000000; |
DF_1_STUBMCST Elbrus general purpose hardware architecture |
pub const DF_1_STUB = 0x04000000; |
DF_1_PIECyan Technology eCOG16 family |
pub const DF_1_PIE = 0x08000000; |
VERSYM_HIDDENNational Semiconductor CompactRISC CR16 16-bit microprocessor |
pub const VERSYM_HIDDEN = 0x8000; |
VERSYM_VERSIONFreescale Extended Time Processing Unit |
pub const VERSYM_VERSION = 0x7fff; |
VER_NDX_LOCALInfineon Technologies SLE9X core |
/// Symbol is local pub const VER_NDX_LOCAL = 0; /// Symbol is global |
VER_NDX_GLOBALIntel L10M |
pub const VER_NDX_GLOBAL = 1; /// Beginning of reserved entries |
VER_NDX_LORESERVEIntel K10M |
pub const VER_NDX_LORESERVE = 0xff00; /// Symbol is to be eliminated |
VER_NDX_ELIMINATEARM AArch64 |
pub const VER_NDX_ELIMINATE = 0xff01; |
VER_FLG_BASEAtmel Corporation 32-bit microprocessor family |
/// Version definition of the file itself pub const VER_FLG_BASE = 1; /// Weak version identifier |
VER_FLG_WEAKSTMicroeletronics STM8 8-bit microcontroller |
pub const VER_FLG_WEAK = 2; |
PT_NULLTilera TILE64 multicore architecture family |
/// Program header table entry unused pub const PT_NULL = 0; /// Loadable program segment |
PT_LOADTilera TILEPro multicore architecture family |
pub const PT_LOAD = 1; /// Dynamic linking information |
PT_DYNAMICNVIDIA CUDA architecture |
pub const PT_DYNAMIC = 2; /// Program interpreter |
PT_INTERPTilera TILE-Gx multicore architecture family |
pub const PT_INTERP = 3; /// Auxiliary information |
PT_NOTECloudShield architecture family |
pub const PT_NOTE = 4; /// Reserved |
PT_SHLIBKIPO-KAIST Core-A 1st generation processor family |
pub const PT_SHLIB = 5; /// Entry for header table itself |
PT_PHDRKIPO-KAIST Core-A 2nd generation processor family |
pub const PT_PHDR = 6; /// Thread-local storage segment |
PT_TLSSynopsys ARCompact V2 |
pub const PT_TLS = 7; /// Number of defined types |
PT_NUMOpen8 8-bit RISC soft processor core |
pub const PT_NUM = 8; /// Start of OS-specific |
PT_LOOSRenesas RL78 family |
pub const PT_LOOS = 0x60000000; /// GCC .eh_frame_hdr segment |
PT_GNU_EH_FRAMEBroadcom VideoCore V processor |
pub const PT_GNU_EH_FRAME = 0x6474e550; /// Indicates stack executability |
PT_GNU_STACKRenesas 78KOR family |
pub const PT_GNU_STACK = 0x6474e551; /// Read-only after relocation |
PT_GNU_RELROFreescale 56800EX Digital Signal Controller (DSC) |
pub const PT_GNU_RELRO = 0x6474e552; |
PT_LOSUNWBeyond BA1 CPU architecture |
pub const PT_LOSUNW = 0x6ffffffa; /// Sun specific segment |
PT_SUNWBSSBeyond BA2 CPU architecture |
pub const PT_SUNWBSS = 0x6ffffffa; /// Stack segment |
PT_SUNWSTACKXMOS xCORE processor family |
pub const PT_SUNWSTACK = 0x6ffffffb; |
PT_HISUNWMicrochip 8-bit PIC(r) family |
pub const PT_HISUNW = 0x6fffffff; /// End of OS-specific |
PT_HIOSReserved by Intel |
pub const PT_HIOS = 0x6fffffff; /// Start of processor-specific |
PT_LOPROCReserved by Intel |
pub const PT_LOPROC = 0x70000000; /// End of processor-specific |
PT_HIPROCReserved by Intel |
pub const PT_HIPROC = 0x7fffffff; |
SHT_NULLReserved by Intel |
/// Section header table entry unused pub const SHT_NULL = 0; /// Program data |
SHT_PROGBITSReserved by Intel |
pub const SHT_PROGBITS = 1; /// Symbol table |
SHT_SYMTABKM211 KM32 32-bit processor |
pub const SHT_SYMTAB = 2; /// String table |
SHT_STRTABKM211 KMX32 32-bit processor |
pub const SHT_STRTAB = 3; /// Relocation entries with addends |
SHT_RELAKM211 KMX16 16-bit processor |
pub const SHT_RELA = 4; /// Symbol hash table |
SHT_HASHKM211 KMX8 8-bit processor |
pub const SHT_HASH = 5; /// Dynamic linking information |
SHT_DYNAMICKM211 KVARC processor |
pub const SHT_DYNAMIC = 6; /// Notes |
SHT_NOTEPaneve CDP architecture family |
pub const SHT_NOTE = 7; /// Program space with no data (bss) |
SHT_NOBITSCognitive Smart Memory Processor |
pub const SHT_NOBITS = 8; /// Relocation entries, no addends |
SHT_RELiCelero CoolEngine |
pub const SHT_REL = 9; /// Reserved |
SHT_SHLIBNanoradio Optimized RISC |
pub const SHT_SHLIB = 10; /// Dynamic linker symbol table |
SHT_DYNSYMCSR Kalimba architecture family |
pub const SHT_DYNSYM = 11; /// Array of constructors |
SHT_INIT_ARRAYAMD GPU architecture |
pub const SHT_INIT_ARRAY = 14; /// Array of destructors |
SHT_FINI_ARRAYRISC-V |
pub const SHT_FINI_ARRAY = 15; /// Array of pre-constructors |
SHT_PREINIT_ARRAYLanai 32-bit processor |
pub const SHT_PREINIT_ARRAY = 16; /// Section group |
SHT_GROUPLinux kernel bpf virtual machine |
pub const SHT_GROUP = 17; /// Extended section indices |
SHT_SYMTAB_SHNDXC-SKY |
pub const SHT_SYMTAB_SHNDX = 18; /// Start of OS-specific |
SHT_LOOSFujitsu FR-V |
pub const SHT_LOOS = 0x60000000; /// LLVM address-significance table |
SHT_LLVM_ADDRSIGSection data should be writable during execution. |
pub const SHT_LLVM_ADDRSIG = 0x6fff4c03; /// GNU hash table |
SHT_GNU_HASHSection occupies memory during program execution. |
pub const SHT_GNU_HASH = 0x6ffffff6; /// GNU version definition table |
SHT_GNU_VERDEFSection contains executable machine instructions. |
pub const SHT_GNU_VERDEF = 0x6ffffffd; /// GNU needed versions table |
SHT_GNU_VERNEEDThe data in this section may be merged. |
pub const SHT_GNU_VERNEED = 0x6ffffffe; /// GNU symbol version table |
SHT_GNU_VERSYMThe data in this section is null-terminated strings. |
pub const SHT_GNU_VERSYM = 0x6fffffff; /// End of OS-specific |
SHT_HIOSA field in this section holds a section header table index. |
pub const SHT_HIOS = 0x6fffffff; /// Start of processor-specific |
SHT_LOPROCAdds special ordering requirements for link editors. |
pub const SHT_LOPROC = 0x70000000; /// Unwind information |
SHT_X86_64_UNWINDThis section requires special OS-specific processing to avoid incorrect behavior. |
pub const SHT_X86_64_UNWIND = 0x70000001; /// End of processor-specific |
SHT_HIPROCThis section is a member of a section group. |
pub const SHT_HIPROC = 0x7fffffff; /// Start of application-specific |
SHT_LOUSERThis section holds Thread-Local Storage. |
pub const SHT_LOUSER = 0x80000000; /// End of application-specific |
SHT_HIUSERIdentifies a section containing compressed data. |
pub const SHT_HIUSER = 0xffffffff; |
NT_GNU_BUILD_IDNot to be GCed by the linker |
// Note type for .note.gnu.build_id pub const NT_GNU_BUILD_ID = 3; |
STB_LOCALThis section is excluded from the final executable or shared library. |
/// Local symbol pub const STB_LOCAL = 0; /// Global symbol |
STB_GLOBALStart of target-specific flags. |
pub const STB_GLOBAL = 1; /// Weak symbol |
STB_WEAKBits indicating processor-specific flags. |
pub const STB_WEAK = 2; /// Number of defined types |
STB_NUMAll sections with the "d" flag are grouped together by the linker to form the data section and the dp register is set to the start of the section by the boot code. |
pub const STB_NUM = 3; /// Start of OS-specific |
STB_LOOSAll sections with the "c" flag are grouped together by the linker to form the constant pool and the cp register is set to the start of the constant pool by the boot code. |
pub const STB_LOOS = 10; /// Unique symbol |
STB_GNU_UNIQUEIf an object file section does not have this flag set, then it may not hold more than 2GB and can be freely referred to in objects using smaller code models. Otherwise, only objects using larger code models can refer to them. For example, a medium code model object can refer to data in a section that sets this flag besides being able to refer to data in a section that does not set it; likewise, a small code model object can refer only to code in a section that does not set this flag. |
pub const STB_GNU_UNIQUE = 10; /// End of OS-specific |
STB_HIOSAll sections with the GPREL flag are grouped into a global data area for faster accesses |
pub const STB_HIOS = 12; /// Start of processor-specific |
STB_LOPROCSection contains text/data which may be replicated in other sections. Linker must retain only one copy. |
pub const STB_LOPROC = 13; /// End of processor-specific |
STB_HIPROCLinker must generate implicit hidden weak names. |
pub const STB_HIPROC = 15; |
STB_MIPS_SPLIT_COMMONSection data local to process. |
pub const STB_MIPS_SPLIT_COMMON = 13; |
STT_NOTYPEDo not strip this section. |
/// Symbol type is unspecified pub const STT_NOTYPE = 0; /// Symbol is a data object |
STT_OBJECTSection must be part of global data area. |
pub const STT_OBJECT = 1; /// Symbol is a code object |
STT_FUNCThis section should be merged. |
pub const STT_FUNC = 2; /// Symbol associated with a section |
STT_SECTIONAddress size to be inferred from section entry size. |
pub const STT_SECTION = 3; /// Symbol's name is file name |
STT_FILESection data is string data by default. |
pub const STT_FILE = 4; /// Symbol is a common data object |
STT_COMMONMake code section unreadable when in execute-only mode |
pub const STT_COMMON = 5; /// Symbol is thread-local data object |
STT_TLSExecute |
pub const STT_TLS = 6; /// Number of defined types |
STT_NUMWrite |
pub const STT_NUM = 7; /// Start of OS-specific |
STT_LOOSRead |
pub const STT_LOOS = 10; /// Symbol is indirect code object |
STT_GNU_IFUNCBits for operating system-specific semantics. |
pub const STT_GNU_IFUNC = 10; /// End of OS-specific |
STT_HIOSBits for processor-specific semantics. |
pub const STT_HIOS = 12; /// Start of processor-specific |
STT_LOPROCUndefined section |
pub const STT_LOPROC = 13; /// End of processor-specific |
STT_HIPROCStart of reserved indices |
pub const STT_HIPROC = 15; |
STT_SPARC_REGISTERStart of processor-specific |
pub const STT_SPARC_REGISTER = 13; |
STT_PARISC_MILLICODEEnd of processor-specific |
pub const STT_PARISC_MILLICODE = 13; |
STT_HP_OPAQUEAssociated symbol is absolute |
pub const STT_HP_OPAQUE = (STT_LOOS + 0x1); |
STT_HP_STUBAssociated symbol is common |
pub const STT_HP_STUB = (STT_LOOS + 0x2); |
STT_ARM_TFUNCEnd of reserved indices |
pub const STT_ARM_TFUNC = STT_LOPROC; |
STT_ARM_16BITAMD x86-64 relocations. No reloc |
pub const STT_ARM_16BIT = STT_HIPROC; |
MAGICDirect 64 bit |
pub const MAGIC = "\x7fELF"; |
ETPC relative 32 bit signed |
/// File types pub const ET = enum(u16) { /// No file type NONE = 0, |
LOPROC32 bit GOT entry |
/// Relocatable file REL = 1, |
HIPROC32 bit PLT address |
/// Executable file EXEC = 2, |
HeaderCopy symbol at runtime |
/// Shared object file DYN = 3, |
program_header_iterator()Create GOT entry |
/// Core file CORE = 4, |
section_header_iterator()Create PLT entry |
/// Beginning of processor-specific codes pub const LOPROC = 0xff00; |
read()Adjust by program base |
/// Processor-specific pub const HIPROC = 0xffff; }; |
parse()32 bit signed PC relative offset to GOT |
/// All integers are native endian. pub const Header = struct { endian: std.builtin.Endian, machine: EM, is_64: bool, entry: u64, phoff: u64, shoff: u64, phentsize: u16, phnum: u16, shentsize: u16, shnum: u16, shstrndx: u16, |
ProgramHeaderIterator()Direct 32 bit zero extended |
pub fn program_header_iterator(self: Header, parse_source: anytype) ProgramHeaderIterator(@TypeOf(parse_source)) { return ProgramHeaderIterator(@TypeOf(parse_source)){ .elf_header = self, .parse_source = parse_source, }; } |
next()Direct 32 bit sign extended |
pub fn section_header_iterator(self: Header, parse_source: anytype) SectionHeaderIterator(@TypeOf(parse_source)) { return SectionHeaderIterator(@TypeOf(parse_source)){ .elf_header = self, .parse_source = parse_source, }; } |
SectionHeaderIterator()Direct 16 bit zero extended |
pub fn read(parse_source: anytype) !Header { var hdr_buf: [@sizeOf(Elf64_Ehdr)]u8 align(@alignOf(Elf64_Ehdr)) = undefined; try parse_source.seekableStream().seekTo(0); try parse_source.reader().readNoEof(&hdr_buf); return Header.parse(&hdr_buf); } |
next()16 bit sign extended pc relative |
pub fn parse(hdr_buf: *align(@alignOf(Elf64_Ehdr)) const [@sizeOf(Elf64_Ehdr)]u8) !Header { const hdr32 = @as(*const Elf32_Ehdr, @ptrCast(hdr_buf)); const hdr64 = @as(*const Elf64_Ehdr, @ptrCast(hdr_buf)); if (!mem.eql(u8, hdr32.e_ident[0..4], MAGIC)) return error.InvalidElfMagic; if (hdr32.e_ident[EI_VERSION] != 1) return error.InvalidElfVersion; |
int()Direct 8 bit sign extended |
const endian: std.builtin.Endian = switch (hdr32.e_ident[EI_DATA]) { ELFDATA2LSB => .Little, ELFDATA2MSB => .Big, else => return error.InvalidElfEndian, }; const need_bswap = endian != native_endian; |
int32()8 bit sign extended pc relative |
const is_64 = switch (hdr32.e_ident[EI_CLASS]) { ELFCLASS32 => false, ELFCLASS64 => true, else => return error.InvalidElfClass, }; |
EI_NIDENTID of module containing symbol |
const machine = if (need_bswap) blk: { const value = @intFromEnum(hdr32.e_machine); break :blk @as(EM, @enumFromInt(@byteSwap(value))); } else hdr32.e_machine; |
EI_CLASSOffset in module's TLS block |
return @as(Header, .{ .endian = endian, .machine = machine, .is_64 = is_64, .entry = int(is_64, need_bswap, hdr32.e_entry, hdr64.e_entry), .phoff = int(is_64, need_bswap, hdr32.e_phoff, hdr64.e_phoff), .shoff = int(is_64, need_bswap, hdr32.e_shoff, hdr64.e_shoff), .phentsize = int(is_64, need_bswap, hdr32.e_phentsize, hdr64.e_phentsize), .phnum = int(is_64, need_bswap, hdr32.e_phnum, hdr64.e_phnum), .shentsize = int(is_64, need_bswap, hdr32.e_shentsize, hdr64.e_shentsize), .shnum = int(is_64, need_bswap, hdr32.e_shnum, hdr64.e_shnum), .shstrndx = int(is_64, need_bswap, hdr32.e_shstrndx, hdr64.e_shstrndx), }); } }; |
ELFCLASSNONEOffset in initial TLS block |
pub fn ProgramHeaderIterator(comptime ParseSource: anytype) type { return struct { elf_header: Header, parse_source: ParseSource, index: usize = 0, |
ELFCLASS3232 bit signed PC relative offset to two GOT entries for GD symbol |
pub fn next(self: *@This()) !?Elf64_Phdr { if (self.index >= self.elf_header.phnum) return null; defer self.index += 1; |
ELFCLASS6432 bit signed PC relative offset to two GOT entries for LD symbol |
if (self.elf_header.is_64) { var phdr: Elf64_Phdr = undefined; const offset = self.elf_header.phoff + @sizeOf(@TypeOf(phdr)) * self.index; try self.parse_source.seekableStream().seekTo(offset); try self.parse_source.reader().readNoEof(mem.asBytes(&phdr)); |
ELFCLASSNUMOffset in TLS block |
// ELF endianness matches native endianness. if (self.elf_header.endian == native_endian) return phdr; |
EI_DATA32 bit signed PC relative offset to GOT entry for IE symbol |
// Convert fields to native endianness. mem.byteSwapAllFields(Elf64_Phdr, &phdr); return phdr; } |
ELFDATANONEOffset in initial TLS block |
var phdr: Elf32_Phdr = undefined; const offset = self.elf_header.phoff + @sizeOf(@TypeOf(phdr)) * self.index; try self.parse_source.seekableStream().seekTo(offset); try self.parse_source.reader().readNoEof(mem.asBytes(&phdr)); |
ELFDATA2LSBPC relative 64 bit |
// ELF endianness does NOT match native endianness. if (self.elf_header.endian != native_endian) { // Convert fields to native endianness. mem.byteSwapAllFields(Elf32_Phdr, &phdr); } |
ELFDATA2MSB64 bit offset to GOT |
// Convert 32-bit header to 64-bit. return Elf64_Phdr{ .p_type = phdr.p_type, .p_offset = phdr.p_offset, .p_vaddr = phdr.p_vaddr, .p_paddr = phdr.p_paddr, .p_filesz = phdr.p_filesz, .p_memsz = phdr.p_memsz, .p_flags = phdr.p_flags, .p_align = phdr.p_align, }; } }; } |
ELFDATANUM32 bit signed pc relative offset to GOT |
pub fn SectionHeaderIterator(comptime ParseSource: anytype) type { return struct { elf_header: Header, parse_source: ParseSource, index: usize = 0, |
EI_VERSION64 bit GOT entry offset |
pub fn next(self: *@This()) !?Elf64_Shdr { if (self.index >= self.elf_header.shnum) return null; defer self.index += 1; |
Elf32_Half64 bit PC relative offset to GOT entry |
if (self.elf_header.is_64) { var shdr: Elf64_Shdr = undefined; const offset = self.elf_header.shoff + @sizeOf(@TypeOf(shdr)) * self.index; try self.parse_source.seekableStream().seekTo(offset); try self.parse_source.reader().readNoEof(mem.asBytes(&shdr)); |
Elf64_Half64 bit PC relative offset to GOT |
// ELF endianness matches native endianness. if (self.elf_header.endian == native_endian) return shdr; |
Elf32_WordLike GOT64, says PLT entry needed |
// Convert fields to native endianness. mem.byteSwapAllFields(Elf64_Shdr, &shdr); return shdr; } |
Elf32_Sword64-bit GOT relative offset to PLT entry |
var shdr: Elf32_Shdr = undefined; const offset = self.elf_header.shoff + @sizeOf(@TypeOf(shdr)) * self.index; try self.parse_source.seekableStream().seekTo(offset); try self.parse_source.reader().readNoEof(mem.asBytes(&shdr)); |
Elf64_WordSize of symbol plus 32-bit addend |
// ELF endianness does NOT match native endianness. if (self.elf_header.endian != native_endian) { // Convert fields to native endianness. mem.byteSwapAllFields(Elf32_Shdr, &shdr); } |
Elf64_SwordSize of symbol plus 64-bit addend |
// Convert 32-bit header to 64-bit. return Elf64_Shdr{ .sh_name = shdr.sh_name, .sh_type = shdr.sh_type, .sh_flags = shdr.sh_flags, .sh_addr = shdr.sh_addr, .sh_offset = shdr.sh_offset, .sh_size = shdr.sh_size, .sh_link = shdr.sh_link, .sh_info = shdr.sh_info, .sh_addralign = shdr.sh_addralign, .sh_entsize = shdr.sh_entsize, }; } }; } |
Elf32_XwordGOT offset for TLS descriptor |
pub fn int(is_64: bool, need_bswap: bool, int_32: anytype, int_64: anytype) @TypeOf(int_64) { if (is_64) { if (need_bswap) { return @byteSwap(int_64); } else { return int_64; } } else { return int32(need_bswap, int_32, @TypeOf(int_64)); } } |
Elf32_SxwordMarker for call through TLS descriptor |
pub fn int32(need_bswap: bool, int_32: anytype, comptime Int64: anytype) Int64 { if (need_bswap) { return @byteSwap(int_32); } else { return int_32; } } |
Elf64_XwordTLS descriptor |
pub const EI_NIDENT = 16; |
Elf64_SxwordAdjust indirectly by program base |
pub const EI_CLASS = 4; pub const ELFCLASSNONE = 0; pub const ELFCLASS32 = 1; pub const ELFCLASS64 = 2; pub const ELFCLASSNUM = 3; |
Elf32_Addr64-bit adjust by program base |
pub const EI_DATA = 5; pub const ELFDATANONE = 0; pub const ELFDATA2LSB = 1; pub const ELFDATA2MSB = 2; pub const ELFDATANUM = 3; |
Elf64_Addr39 Reserved was R_X86_64_PC32_BND 40 Reserved was R_X86_64_PLT32_BND Load from 32 bit signed pc relative offset to GOT entry without REX prefix, relaxable |
pub const EI_VERSION = 6; |
Elf32_OffLoad from 32 bit signed PC relative offset to GOT entry with REX prefix, relaxable |
pub const Elf32_Half = u16; pub const Elf64_Half = u16; pub const Elf32_Word = u32; pub const Elf32_Sword = i32; pub const Elf64_Word = u32; pub const Elf64_Sword = i32; pub const Elf32_Xword = u64; pub const Elf32_Sxword = i64; pub const Elf64_Xword = u64; pub const Elf64_Sxword = i64; pub const Elf32_Addr = u32; pub const Elf64_Addr = u64; pub const Elf32_Off = u32; |
Elf64_Off |
pub const Elf64_Off = u64; |
Elf32_Section |
pub const Elf32_Section = u16; |
Elf64_Section |
pub const Elf64_Section = u16; |
Elf32_Versym |
pub const Elf32_Versym = Elf32_Half; |
Elf64_Versym |
pub const Elf64_Versym = Elf64_Half; |
Elf32_Ehdr |
pub const Elf32_Ehdr = extern struct { e_ident: [EI_NIDENT]u8, e_type: ET, e_machine: EM, e_version: Elf32_Word, e_entry: Elf32_Addr, e_phoff: Elf32_Off, e_shoff: Elf32_Off, e_flags: Elf32_Word, e_ehsize: Elf32_Half, e_phentsize: Elf32_Half, e_phnum: Elf32_Half, e_shentsize: Elf32_Half, e_shnum: Elf32_Half, e_shstrndx: Elf32_Half, }; |
Elf64_Ehdr |
pub const Elf64_Ehdr = extern struct { e_ident: [EI_NIDENT]u8, e_type: ET, e_machine: EM, e_version: Elf64_Word, e_entry: Elf64_Addr, e_phoff: Elf64_Off, e_shoff: Elf64_Off, e_flags: Elf64_Word, e_ehsize: Elf64_Half, e_phentsize: Elf64_Half, e_phnum: Elf64_Half, e_shentsize: Elf64_Half, e_shnum: Elf64_Half, e_shstrndx: Elf64_Half, }; |
Elf32_Phdr |
pub const Elf32_Phdr = extern struct { p_type: Elf32_Word, p_offset: Elf32_Off, p_vaddr: Elf32_Addr, p_paddr: Elf32_Addr, p_filesz: Elf32_Word, p_memsz: Elf32_Word, p_flags: Elf32_Word, p_align: Elf32_Word, }; |
Elf64_Phdr |
pub const Elf64_Phdr = extern struct { p_type: Elf64_Word, p_flags: Elf64_Word, p_offset: Elf64_Off, p_vaddr: Elf64_Addr, p_paddr: Elf64_Addr, p_filesz: Elf64_Xword, p_memsz: Elf64_Xword, p_align: Elf64_Xword, }; |
Elf32_Shdr |
pub const Elf32_Shdr = extern struct { sh_name: Elf32_Word, sh_type: Elf32_Word, sh_flags: Elf32_Word, sh_addr: Elf32_Addr, sh_offset: Elf32_Off, sh_size: Elf32_Word, sh_link: Elf32_Word, sh_info: Elf32_Word, sh_addralign: Elf32_Word, sh_entsize: Elf32_Word, }; |
Elf64_Shdr |
pub const Elf64_Shdr = extern struct { sh_name: Elf64_Word, sh_type: Elf64_Word, sh_flags: Elf64_Xword, sh_addr: Elf64_Addr, sh_offset: Elf64_Off, sh_size: Elf64_Xword, sh_link: Elf64_Word, sh_info: Elf64_Word, sh_addralign: Elf64_Xword, sh_entsize: Elf64_Xword, }; |
Elf32_Chdr |
pub const Elf32_Chdr = extern struct { ch_type: COMPRESS, ch_size: Elf32_Word, ch_addralign: Elf32_Word, }; |
Elf64_Chdr |
pub const Elf64_Chdr = extern struct { ch_type: COMPRESS, ch_reserved: Elf64_Word = 0, ch_size: Elf64_Xword, ch_addralign: Elf64_Xword, }; |
Elf32_Sym |
pub const Elf32_Sym = extern struct { st_name: Elf32_Word, st_value: Elf32_Addr, st_size: Elf32_Word, st_info: u8, st_other: u8, st_shndx: Elf32_Section, |
st_type() |
|
st_type() |
pub inline fn st_type(self: @This()) u4 { return @as(u4, @truncate(self.st_info)); } |
st_bind() |
pub inline fn st_bind(self: @This()) u4 { return @as(u4, @truncate(self.st_info >> 4)); } }; pub const Elf64_Sym = extern struct { st_name: Elf64_Word, st_info: u8, st_other: u8, st_shndx: Elf64_Section, st_value: Elf64_Addr, st_size: Elf64_Xword, |
st_type() |
pub inline fn st_type(self: @This()) u4 { return @as(u4, @truncate(self.st_info)); } |
st_bind() |
pub inline fn st_bind(self: @This()) u4 { return @as(u4, @truncate(self.st_info >> 4)); } }; |
Elf32_Syminfo |
pub const Elf32_Syminfo = extern struct { si_boundto: Elf32_Half, si_flags: Elf32_Half, }; |
Elf64_Syminfo |
pub const Elf64_Syminfo = extern struct { si_boundto: Elf64_Half, si_flags: Elf64_Half, }; |
Elf32_Rel |
pub const Elf32_Rel = extern struct { r_offset: Elf32_Addr, r_info: Elf32_Word, |
r_sym() |
|
r_sym() |
pub inline fn r_sym(self: @This()) u24 { return @as(u24, @truncate(self.r_info >> 8)); } |
r_type() |
pub inline fn r_type(self: @This()) u8 { return @as(u8, @truncate(self.r_info)); } }; pub const Elf64_Rel = extern struct { r_offset: Elf64_Addr, r_info: Elf64_Xword, |
r_sym() |
|
r_sym() |
pub inline fn r_sym(self: @This()) u32 { return @as(u32, @truncate(self.r_info >> 32)); } |
r_type() |
pub inline fn r_type(self: @This()) u32 { return @as(u32, @truncate(self.r_info)); } }; pub const Elf32_Rela = extern struct { r_offset: Elf32_Addr, r_info: Elf32_Word, r_addend: Elf32_Sword, |
r_sym() |
pub inline fn r_sym(self: @This()) u24 { return @as(u24, @truncate(self.r_info >> 8)); } |
r_type() |
pub inline fn r_type(self: @This()) u8 { return @as(u8, @truncate(self.r_info)); } }; |
Elf64_Rela |
pub const Elf64_Rela = extern struct { r_offset: Elf64_Addr, r_info: Elf64_Xword, r_addend: Elf64_Sxword, |
r_sym() |
pub inline fn r_sym(self: @This()) u32 { return @as(u32, @truncate(self.r_info >> 32)); } |
r_type() |
pub inline fn r_type(self: @This()) u32 { return @as(u32, @truncate(self.r_info)); } }; |
Elf32_Dyn |
pub const Elf32_Dyn = extern struct { d_tag: Elf32_Sword, d_val: Elf32_Addr, }; |
Elf64_Dyn |
pub const Elf64_Dyn = extern struct { d_tag: Elf64_Sxword, d_val: Elf64_Addr, }; |
Elf32_Verdef |
pub const Elf32_Verdef = extern struct { vd_version: Elf32_Half, vd_flags: Elf32_Half, vd_ndx: Elf32_Half, vd_cnt: Elf32_Half, vd_hash: Elf32_Word, vd_aux: Elf32_Word, vd_next: Elf32_Word, }; |
Elf64_Verdef |
pub const Elf64_Verdef = extern struct { vd_version: Elf64_Half, vd_flags: Elf64_Half, vd_ndx: Elf64_Half, vd_cnt: Elf64_Half, vd_hash: Elf64_Word, vd_aux: Elf64_Word, vd_next: Elf64_Word, }; |
Elf32_Verdaux |
pub const Elf32_Verdaux = extern struct { vda_name: Elf32_Word, vda_next: Elf32_Word, }; |
Elf64_Verdaux |
pub const Elf64_Verdaux = extern struct { vda_name: Elf64_Word, vda_next: Elf64_Word, }; |
Elf32_Verneed |
pub const Elf32_Verneed = extern struct { vn_version: Elf32_Half, vn_cnt: Elf32_Half, vn_file: Elf32_Word, vn_aux: Elf32_Word, vn_next: Elf32_Word, }; |
Elf64_Verneed |
pub const Elf64_Verneed = extern struct { vn_version: Elf64_Half, vn_cnt: Elf64_Half, vn_file: Elf64_Word, vn_aux: Elf64_Word, vn_next: Elf64_Word, }; |
Elf32_Vernaux |
pub const Elf32_Vernaux = extern struct { vna_hash: Elf32_Word, vna_flags: Elf32_Half, vna_other: Elf32_Half, vna_name: Elf32_Word, vna_next: Elf32_Word, }; |
Elf64_Vernaux |
pub const Elf64_Vernaux = extern struct { vna_hash: Elf64_Word, vna_flags: Elf64_Half, vna_other: Elf64_Half, vna_name: Elf64_Word, vna_next: Elf64_Word, }; |
Elf32_auxv_t |
pub const Elf32_auxv_t = extern struct { a_type: u32, a_un: extern union { a_val: u32, }, }; |
Elf64_auxv_t |
pub const Elf64_auxv_t = extern struct { a_type: u64, a_un: extern union { a_val: u64, }, }; |
Elf32_Nhdr |
pub const Elf32_Nhdr = extern struct { n_namesz: Elf32_Word, n_descsz: Elf32_Word, n_type: Elf32_Word, }; |
Elf64_Nhdr |
pub const Elf64_Nhdr = extern struct { n_namesz: Elf64_Word, n_descsz: Elf64_Word, n_type: Elf64_Word, }; |
Elf32_Move |
pub const Elf32_Move = extern struct { m_value: Elf32_Xword, m_info: Elf32_Word, m_poffset: Elf32_Word, m_repeat: Elf32_Half, m_stride: Elf32_Half, }; |
Elf64_Move |
pub const Elf64_Move = extern struct { m_value: Elf64_Xword, m_info: Elf64_Xword, m_poffset: Elf64_Xword, m_repeat: Elf64_Half, m_stride: Elf64_Half, }; |
Elf32_gptab |
pub const Elf32_gptab = extern union { gt_header: extern struct { gt_current_g_value: Elf32_Word, gt_unused: Elf32_Word, }, gt_entry: extern struct { gt_g_value: Elf32_Word, gt_bytes: Elf32_Word, }, }; |
Elf32_RegInfo |
pub const Elf32_RegInfo = extern struct { ri_gprmask: Elf32_Word, ri_cprmask: [4]Elf32_Word, ri_gp_value: Elf32_Sword, }; |
Elf_Options |
pub const Elf_Options = extern struct { kind: u8, size: u8, section: Elf32_Section, info: Elf32_Word, }; |
Elf_Options_Hw |
pub const Elf_Options_Hw = extern struct { hwp_flags1: Elf32_Word, hwp_flags2: Elf32_Word, }; |
Elf32_Lib |
pub const Elf32_Lib = extern struct { l_name: Elf32_Word, l_time_stamp: Elf32_Word, l_checksum: Elf32_Word, l_version: Elf32_Word, l_flags: Elf32_Word, }; |
Elf64_Lib |
pub const Elf64_Lib = extern struct { l_name: Elf64_Word, l_time_stamp: Elf64_Word, l_checksum: Elf64_Word, l_version: Elf64_Word, l_flags: Elf64_Word, }; |
Elf32_Conflict |
pub const Elf32_Conflict = Elf32_Addr; |
Elf_MIPS_ABIFlags_v0 |
pub const Elf_MIPS_ABIFlags_v0 = extern struct { version: Elf32_Half, isa_level: u8, isa_rev: u8, gpr_size: u8, cpr1_size: u8, cpr2_size: u8, fp_abi: u8, isa_ext: Elf32_Word, ases: Elf32_Word, flags1: Elf32_Word, flags2: Elf32_Word, }; |
Auxv |
comptime { assert(@sizeOf(Elf32_Ehdr) == 52); assert(@sizeOf(Elf64_Ehdr) == 64); |
Ehdr |
assert(@sizeOf(Elf32_Phdr) == 32); assert(@sizeOf(Elf64_Phdr) == 56); |
Phdr |
assert(@sizeOf(Elf32_Shdr) == 40); assert(@sizeOf(Elf64_Shdr) == 64); } |
Dyn |
pub const Auxv = switch (@sizeOf(usize)) { 4 => Elf32_auxv_t, 8 => Elf64_auxv_t, else => @compileError("expected pointer size of 32 or 64"), }; pub const Ehdr = switch (@sizeOf(usize)) { 4 => Elf32_Ehdr, 8 => Elf64_Ehdr, else => @compileError("expected pointer size of 32 or 64"), }; pub const Phdr = switch (@sizeOf(usize)) { 4 => Elf32_Phdr, 8 => Elf64_Phdr, else => @compileError("expected pointer size of 32 or 64"), }; pub const Dyn = switch (@sizeOf(usize)) { 4 => Elf32_Dyn, 8 => Elf64_Dyn, else => @compileError("expected pointer size of 32 or 64"), }; |
Rel |
pub const Rel = switch (@sizeOf(usize)) { 4 => Elf32_Rel, 8 => Elf64_Rel, else => @compileError("expected pointer size of 32 or 64"), }; |
Rela |
pub const Rela = switch (@sizeOf(usize)) { 4 => Elf32_Rela, 8 => Elf64_Rela, else => @compileError("expected pointer size of 32 or 64"), }; |
Shdr |
pub const Shdr = switch (@sizeOf(usize)) { 4 => Elf32_Shdr, 8 => Elf64_Shdr, else => @compileError("expected pointer size of 32 or 64"), }; |
Chdr |
pub const Chdr = switch (@sizeOf(usize)) { 4 => Elf32_Chdr, 8 => Elf64_Chdr, else => @compileError("expected pointer size of 32 or 64"), }; |
Sym |
pub const Sym = switch (@sizeOf(usize)) { 4 => Elf32_Sym, 8 => Elf64_Sym, else => @compileError("expected pointer size of 32 or 64"), }; |
Verdef |
pub const Verdef = switch (@sizeOf(usize)) { 4 => Elf32_Verdef, 8 => Elf64_Verdef, else => @compileError("expected pointer size of 32 or 64"), }; |
Verdaux |
pub const Verdaux = switch (@sizeOf(usize)) { 4 => Elf32_Verdaux, 8 => Elf64_Verdaux, else => @compileError("expected pointer size of 32 or 64"), }; |
Addr |
pub const Addr = switch (@sizeOf(usize)) { 4 => Elf32_Addr, 8 => Elf64_Addr, else => @compileError("expected pointer size of 32 or 64"), }; |
Half |
pub const Half = switch (@sizeOf(usize)) { 4 => Elf32_Half, 8 => Elf64_Half, else => @compileError("expected pointer size of 32 or 64"), }; |
EM |
/// Machine architectures. /// /// See current registered ELF machine architectures at: /// http://www.sco.com/developers/gabi/latest/ch4.eheader.html pub const EM = enum(u16) { /// No machine NONE = 0, |
toTargetCpuArch() |
/// AT&T WE 32100 M32 = 1, |
SHF_WRITE |
/// SPARC SPARC = 2, |
SHF_ALLOC |
/// Intel 386 @"386" = 3, |
SHF_EXECINSTR |
/// Motorola 68000 @"68K" = 4, |
SHF_MERGE |
/// Motorola 88000 @"88K" = 5, |
SHF_STRINGS |
/// Intel MCU IAMCU = 6, |
SHF_INFO_LINK |
/// Intel 80860 @"860" = 7, |
SHF_LINK_ORDER |
/// MIPS R3000 MIPS = 8, |
SHF_OS_NONCONFORMING |
/// IBM System/370 S370 = 9, |
SHF_GROUP |
/// MIPS RS3000 Little-endian MIPS_RS3_LE = 10, |
SHF_TLS |
/// SPU Mark II SPU_2 = 13, |
SHF_COMPRESSED |
/// Hewlett-Packard PA-RISC PARISC = 15, |
SHF_GNU_RETAIN |
/// Fujitsu VPP500 VPP500 = 17, |
SHF_EXCLUDE |
/// Enhanced instruction set SPARC SPARC32PLUS = 18, |
SHF_MASKOS |
/// Intel 80960 @"960" = 19, |
SHF_MASKPROC |
/// PowerPC PPC = 20, |
XCORE_SHF_DP_SECTION |
/// PowerPC64 PPC64 = 21, |
XCORE_SHF_CP_SECTION |
/// IBM System/390 S390 = 22, |
SHF_X86_64_LARGE |
/// IBM SPU/SPC SPU = 23, |
SHF_HEX_GPREL |
/// NEC V800 V800 = 36, |
SHF_MIPS_NODUPES |
/// Fujitsu FR20 FR20 = 37, |
SHF_MIPS_NAMES |
/// TRW RH-32 RH32 = 38, |
SHF_MIPS_LOCAL |
/// Motorola RCE RCE = 39, |
SHF_MIPS_NOSTRIP |
/// ARM ARM = 40, |
SHF_MIPS_GPREL |
/// DEC Alpha ALPHA = 41, |
SHF_MIPS_MERGE |
/// Hitachi SH SH = 42, |
SHF_MIPS_ADDR |
/// SPARC V9 SPARCV9 = 43, |
SHF_MIPS_STRING |
/// Siemens TriCore TRICORE = 44, |
SHF_ARM_PURECODE |
/// Argonaut RISC Core ARC = 45, |
PF_X |
/// Hitachi H8/300 H8_300 = 46, |
PF_W |
/// Hitachi H8/300H H8_300H = 47, |
PF_R |
/// Hitachi H8S H8S = 48, |
PF_MASKOS |
/// Hitachi H8/500 H8_500 = 49, |
PF_MASKPROC |
/// Intel IA-64 processor architecture IA_64 = 50, |
SHN_UNDEF |
/// Stanford MIPS-X MIPS_X = 51, |
SHN_LORESERVE |
/// Motorola ColdFire COLDFIRE = 52, |
SHN_LOPROC |
/// Motorola M68HC12 @"68HC12" = 53, |
SHN_HIPROC |
/// Fujitsu MMA Multimedia Accelerator MMA = 54, |
SHN_LIVEPATCH |
/// Siemens PCP PCP = 55, |
SHN_ABS |
/// Sony nCPU embedded RISC processor NCPU = 56, |
SHN_COMMON |
/// Denso NDR1 microprocessor NDR1 = 57, |
SHN_HIRESERVE |
/// Motorola Star*Core processor STARCORE = 58, |
COMPRESS |
/// Toyota ME16 processor ME16 = 59, |
R_X86_64_NONE |
/// STMicroelectronics ST100 processor ST100 = 60, |
R_X86_64_64 |
/// Advanced Logic Corp. TinyJ embedded processor family TINYJ = 61, |
R_X86_64_PC32 |
/// AMD x86-64 architecture X86_64 = 62, |
R_X86_64_GOT32 |
/// Sony DSP Processor PDSP = 63, |
R_X86_64_PLT32 |
/// Digital Equipment Corp. PDP-10 PDP10 = 64, |
R_X86_64_COPY |
/// Digital Equipment Corp. PDP-11 PDP11 = 65, |
R_X86_64_GLOB_DAT |
/// Siemens FX66 microcontroller FX66 = 66, |
R_X86_64_JUMP_SLOT |
/// STMicroelectronics ST9+ 8/16 bit microcontroller ST9PLUS = 67, |
R_X86_64_RELATIVE |
/// STMicroelectronics ST7 8-bit microcontroller ST7 = 68, |
R_X86_64_GOTPCREL |
/// Motorola MC68HC16 Microcontroller @"68HC16" = 69, |
R_X86_64_32 |
/// Motorola MC68HC11 Microcontroller @"68HC11" = 70, |
R_X86_64_32S |
/// Motorola MC68HC08 Microcontroller @"68HC08" = 71, |
R_X86_64_16 |
/// Motorola MC68HC05 Microcontroller @"68HC05" = 72, |
R_X86_64_PC16 |
/// Silicon Graphics SVx SVX = 73, |
R_X86_64_8 |
/// STMicroelectronics ST19 8-bit microcontroller ST19 = 74, |
R_X86_64_PC8 |
/// Digital VAX VAX = 75, |
R_X86_64_DTPMOD64 |
/// Axis Communications 32-bit embedded processor CRIS = 76, |
R_X86_64_DTPOFF64 |
/// Infineon Technologies 32-bit embedded processor JAVELIN = 77, |
R_X86_64_TPOFF64 |
/// Element 14 64-bit DSP Processor FIREPATH = 78, |
R_X86_64_TLSGD |
/// LSI Logic 16-bit DSP Processor ZSP = 79, |
R_X86_64_TLSLD |
/// Donald Knuth's educational 64-bit processor MMIX = 80, |
R_X86_64_DTPOFF32 |
/// Harvard University machine-independent object files HUANY = 81, |
R_X86_64_GOTTPOFF |
/// SiTera Prism PRISM = 82, |
R_X86_64_TPOFF32 |
/// Atmel AVR 8-bit microcontroller AVR = 83, |
R_X86_64_PC64 |
/// Fujitsu FR30 FR30 = 84, |
R_X86_64_GOTOFF64 |
/// Mitsubishi D10V D10V = 85, |
R_X86_64_GOTPC32 |
/// Mitsubishi D30V D30V = 86, |
R_X86_64_GOT64 |
/// NEC v850 V850 = 87, |
R_X86_64_GOTPCREL64 |
/// Mitsubishi M32R M32R = 88, |
R_X86_64_GOTPC64 |
/// Matsushita MN10300 MN10300 = 89, |
R_X86_64_GOTPLT64 |
/// Matsushita MN10200 MN10200 = 90, |
R_X86_64_PLTOFF64 |
/// picoJava PJ = 91, |
R_X86_64_SIZE32 |
/// OpenRISC 32-bit embedded processor OPENRISC = 92, |
R_X86_64_SIZE64 |
/// ARC International ARCompact processor (old spelling/synonym: EM_ARC_A5) ARC_COMPACT = 93, |
R_X86_64_GOTPC32_TLSDESC |
/// Tensilica Xtensa Architecture XTENSA = 94, |
R_X86_64_TLSDESC_CALL |
/// Alphamosaic VideoCore processor VIDEOCORE = 95, |
R_X86_64_TLSDESC |
/// Thompson Multimedia General Purpose Processor TMM_GPP = 96, |
R_X86_64_IRELATIVE |
/// National Semiconductor 32000 series NS32K = 97, |
R_X86_64_RELATIVE64 |
/// Tenor Network TPC processor TPC = 98, |
R_X86_64_GOTPCRELX |
/// Trebia SNP 1000 processor SNP1K = 99, |
R_X86_64_REX_GOTPCRELX |
/// STMicroelectronics (www.st.com) ST200 ST200 = 100, |
R_X86_64_NUM |
/// Ubicom IP2xxx microcontroller family IP2K = 101, |
STV |
/// MAX Processor MAX = 102, /// National Semiconductor CompactRISC microprocessor CR = 103, /// Fujitsu F2MC16 F2MC16 = 104, /// Texas Instruments embedded microcontroller msp430 MSP430 = 105, /// Analog Devices Blackfin (DSP) processor BLACKFIN = 106, /// S1C33 Family of Seiko Epson processors SE_C33 = 107, /// Sharp embedded microprocessor SEP = 108, /// Arca RISC Microprocessor ARCA = 109, /// Microprocessor series from PKU-Unity Ltd. and MPRC of Peking University UNICORE = 110, /// eXcess: 16/32/64-bit configurable embedded CPU EXCESS = 111, /// Icera Semiconductor Inc. Deep Execution Processor DXP = 112, /// Altera Nios II soft-core processor ALTERA_NIOS2 = 113, /// National Semiconductor CompactRISC CRX CRX = 114, /// Motorola XGATE embedded processor XGATE = 115, /// Infineon C16x/XC16x processor C166 = 116, /// Renesas M16C series microprocessors M16C = 117, /// Microchip Technology dsPIC30F Digital Signal Controller DSPIC30F = 118, /// Freescale Communication Engine RISC core CE = 119, /// Renesas M32C series microprocessors M32C = 120, /// Altium TSK3000 core TSK3000 = 131, /// Freescale RS08 embedded processor RS08 = 132, /// Analog Devices SHARC family of 32-bit DSP processors SHARC = 133, /// Cyan Technology eCOG2 microprocessor ECOG2 = 134, /// Sunplus S+core7 RISC processor SCORE7 = 135, /// New Japan Radio (NJR) 24-bit DSP Processor DSP24 = 136, /// Broadcom VideoCore III processor VIDEOCORE3 = 137, /// RISC processor for Lattice FPGA architecture LATTICEMICO32 = 138, /// Seiko Epson C17 family SE_C17 = 139, /// The Texas Instruments TMS320C6000 DSP family TI_C6000 = 140, /// The Texas Instruments TMS320C2000 DSP family TI_C2000 = 141, /// The Texas Instruments TMS320C55x DSP family TI_C5500 = 142, /// STMicroelectronics 64bit VLIW Data Signal Processor MMDSP_PLUS = 160, /// Cypress M8C microprocessor CYPRESS_M8C = 161, /// Renesas R32C series microprocessors R32C = 162, /// NXP Semiconductors TriMedia architecture family TRIMEDIA = 163, /// Qualcomm Hexagon processor HEXAGON = 164, /// Intel 8051 and variants @"8051" = 165, /// STMicroelectronics STxP7x family of configurable and extensible RISC processors STXP7X = 166, /// Andes Technology compact code size embedded RISC processor family NDS32 = 167, /// Cyan Technology eCOG1X family ECOG1X = 168, /// Dallas Semiconductor MAXQ30 Core Micro-controllers MAXQ30 = 169, /// New Japan Radio (NJR) 16-bit DSP Processor XIMO16 = 170, /// M2000 Reconfigurable RISC Microprocessor MANIK = 171, /// Cray Inc. NV2 vector architecture CRAYNV2 = 172, /// Renesas RX family RX = 173, /// Imagination Technologies META processor architecture METAG = 174, /// MCST Elbrus general purpose hardware architecture MCST_ELBRUS = 175, /// Cyan Technology eCOG16 family ECOG16 = 176, /// National Semiconductor CompactRISC CR16 16-bit microprocessor CR16 = 177, /// Freescale Extended Time Processing Unit ETPU = 178, /// Infineon Technologies SLE9X core SLE9X = 179, /// Intel L10M L10M = 180, /// Intel K10M K10M = 181, /// ARM AArch64 AARCH64 = 183, /// Atmel Corporation 32-bit microprocessor family AVR32 = 185, /// STMicroeletronics STM8 8-bit microcontroller STM8 = 186, /// Tilera TILE64 multicore architecture family TILE64 = 187, /// Tilera TILEPro multicore architecture family TILEPRO = 188, /// NVIDIA CUDA architecture CUDA = 190, /// Tilera TILE-Gx multicore architecture family TILEGX = 191, /// CloudShield architecture family CLOUDSHIELD = 192, /// KIPO-KAIST Core-A 1st generation processor family COREA_1ST = 193, /// KIPO-KAIST Core-A 2nd generation processor family COREA_2ND = 194, /// Synopsys ARCompact V2 ARC_COMPACT2 = 195, /// Open8 8-bit RISC soft processor core OPEN8 = 196, /// Renesas RL78 family RL78 = 197, /// Broadcom VideoCore V processor VIDEOCORE5 = 198, /// Renesas 78KOR family @"78KOR" = 199, /// Freescale 56800EX Digital Signal Controller (DSC) @"56800EX" = 200, /// Beyond BA1 CPU architecture BA1 = 201, /// Beyond BA2 CPU architecture BA2 = 202, /// XMOS xCORE processor family XCORE = 203, /// Microchip 8-bit PIC(r) family MCHP_PIC = 204, /// Reserved by Intel INTEL205 = 205, /// Reserved by Intel INTEL206 = 206, /// Reserved by Intel INTEL207 = 207, /// Reserved by Intel INTEL208 = 208, /// Reserved by Intel INTEL209 = 209, /// KM211 KM32 32-bit processor KM32 = 210, /// KM211 KMX32 32-bit processor KMX32 = 211, /// KM211 KMX16 16-bit processor KMX16 = 212, /// KM211 KMX8 8-bit processor KMX8 = 213, /// KM211 KVARC processor KVARC = 214, /// Paneve CDP architecture family CDP = 215, /// Cognitive Smart Memory Processor COGE = 216, /// iCelero CoolEngine COOL = 217, /// Nanoradio Optimized RISC NORC = 218, /// CSR Kalimba architecture family CSR_KALIMBA = 219, /// AMD GPU architecture AMDGPU = 224, /// RISC-V RISCV = 243, /// Lanai 32-bit processor LANAI = 244, /// Linux kernel bpf virtual machine BPF = 247, /// C-SKY CSKY = 252, /// Fujitsu FR-V FRV = 0x5441, _, pub fn toTargetCpuArch(em: EM) ?std.Target.Cpu.Arch { return switch (em) { .AVR => .avr, .MSP430 => .msp430, .ARC => .arc, .ARM => .arm, .HEXAGON => .hexagon, .@"68K" => .m68k, .MIPS => .mips, .MIPS_RS3_LE => .mipsel, .PPC => .powerpc, .SPARC => .sparc, .@"386" => .x86, .XCORE => .xcore, .CSR_KALIMBA => .kalimba, .LANAI => .lanai, .AARCH64 => .aarch64, .PPC64 => .powerpc64, .RISCV => .riscv64, .X86_64 => .x86_64, .BPF => .bpfel, .SPARCV9 => .sparc64, .S390 => .s390x, .SPU_2 => .spu_2, // there's many cases we don't (yet) handle, or will never have a // zig target cpu arch equivalent (such as null). else => null, }; } }; /// Section data should be writable during execution. pub const SHF_WRITE = 0x1; /// Section occupies memory during program execution. pub const SHF_ALLOC = 0x2; /// Section contains executable machine instructions. pub const SHF_EXECINSTR = 0x4; /// The data in this section may be merged. pub const SHF_MERGE = 0x10; /// The data in this section is null-terminated strings. pub const SHF_STRINGS = 0x20; /// A field in this section holds a section header table index. pub const SHF_INFO_LINK = 0x40; /// Adds special ordering requirements for link editors. pub const SHF_LINK_ORDER = 0x80; /// This section requires special OS-specific processing to avoid incorrect /// behavior. pub const SHF_OS_NONCONFORMING = 0x100; /// This section is a member of a section group. pub const SHF_GROUP = 0x200; /// This section holds Thread-Local Storage. pub const SHF_TLS = 0x400; /// Identifies a section containing compressed data. pub const SHF_COMPRESSED = 0x800; /// Not to be GCed by the linker pub const SHF_GNU_RETAIN = 0x200000; /// This section is excluded from the final executable or shared library. pub const SHF_EXCLUDE = 0x80000000; /// Start of target-specific flags. pub const SHF_MASKOS = 0x0ff00000; /// Bits indicating processor-specific flags. pub const SHF_MASKPROC = 0xf0000000; /// All sections with the "d" flag are grouped together by the linker to form /// the data section and the dp register is set to the start of the section by /// the boot code. pub const XCORE_SHF_DP_SECTION = 0x10000000; /// All sections with the "c" flag are grouped together by the linker to form /// the constant pool and the cp register is set to the start of the constant /// pool by the boot code. pub const XCORE_SHF_CP_SECTION = 0x20000000; /// If an object file section does not have this flag set, then it may not hold /// more than 2GB and can be freely referred to in objects using smaller code /// models. Otherwise, only objects using larger code models can refer to them. /// For example, a medium code model object can refer to data in a section that /// sets this flag besides being able to refer to data in a section that does /// not set it; likewise, a small code model object can refer only to code in a /// section that does not set this flag. pub const SHF_X86_64_LARGE = 0x10000000; /// All sections with the GPREL flag are grouped into a global data area /// for faster accesses pub const SHF_HEX_GPREL = 0x10000000; /// Section contains text/data which may be replicated in other sections. /// Linker must retain only one copy. pub const SHF_MIPS_NODUPES = 0x01000000; /// Linker must generate implicit hidden weak names. pub const SHF_MIPS_NAMES = 0x02000000; /// Section data local to process. pub const SHF_MIPS_LOCAL = 0x04000000; /// Do not strip this section. pub const SHF_MIPS_NOSTRIP = 0x08000000; /// Section must be part of global data area. pub const SHF_MIPS_GPREL = 0x10000000; /// This section should be merged. pub const SHF_MIPS_MERGE = 0x20000000; /// Address size to be inferred from section entry size. pub const SHF_MIPS_ADDR = 0x40000000; /// Section data is string data by default. pub const SHF_MIPS_STRING = 0x80000000; /// Make code section unreadable when in execute-only mode pub const SHF_ARM_PURECODE = 0x2000000; /// Execute pub const PF_X = 1; /// Write pub const PF_W = 2; /// Read pub const PF_R = 4; /// Bits for operating system-specific semantics. pub const PF_MASKOS = 0x0ff00000; /// Bits for processor-specific semantics. pub const PF_MASKPROC = 0xf0000000; /// Undefined section pub const SHN_UNDEF = 0; /// Start of reserved indices pub const SHN_LORESERVE = 0xff00; /// Start of processor-specific pub const SHN_LOPROC = 0xff00; /// End of processor-specific pub const SHN_HIPROC = 0xff1f; pub const SHN_LIVEPATCH = 0xff20; /// Associated symbol is absolute pub const SHN_ABS = 0xfff1; /// Associated symbol is common pub const SHN_COMMON = 0xfff2; /// End of reserved indices pub const SHN_HIRESERVE = 0xffff; // Legal values for ch_type (compression algorithm). pub const COMPRESS = enum(u32) { ZLIB = 1, ZSTD = 2, LOOS = 0x60000000, HIOS = 0x6fffffff, LOPROC = 0x70000000, HIPROC = 0x7fffffff, _, }; /// AMD x86-64 relocations. /// No reloc pub const R_X86_64_NONE = 0; /// Direct 64 bit pub const R_X86_64_64 = 1; /// PC relative 32 bit signed pub const R_X86_64_PC32 = 2; /// 32 bit GOT entry pub const R_X86_64_GOT32 = 3; /// 32 bit PLT address pub const R_X86_64_PLT32 = 4; /// Copy symbol at runtime pub const R_X86_64_COPY = 5; /// Create GOT entry pub const R_X86_64_GLOB_DAT = 6; /// Create PLT entry pub const R_X86_64_JUMP_SLOT = 7; /// Adjust by program base pub const R_X86_64_RELATIVE = 8; /// 32 bit signed PC relative offset to GOT pub const R_X86_64_GOTPCREL = 9; /// Direct 32 bit zero extended pub const R_X86_64_32 = 10; /// Direct 32 bit sign extended pub const R_X86_64_32S = 11; /// Direct 16 bit zero extended pub const R_X86_64_16 = 12; /// 16 bit sign extended pc relative pub const R_X86_64_PC16 = 13; /// Direct 8 bit sign extended pub const R_X86_64_8 = 14; /// 8 bit sign extended pc relative pub const R_X86_64_PC8 = 15; /// ID of module containing symbol pub const R_X86_64_DTPMOD64 = 16; /// Offset in module's TLS block pub const R_X86_64_DTPOFF64 = 17; /// Offset in initial TLS block pub const R_X86_64_TPOFF64 = 18; /// 32 bit signed PC relative offset to two GOT entries for GD symbol pub const R_X86_64_TLSGD = 19; /// 32 bit signed PC relative offset to two GOT entries for LD symbol pub const R_X86_64_TLSLD = 20; /// Offset in TLS block pub const R_X86_64_DTPOFF32 = 21; /// 32 bit signed PC relative offset to GOT entry for IE symbol pub const R_X86_64_GOTTPOFF = 22; /// Offset in initial TLS block pub const R_X86_64_TPOFF32 = 23; /// PC relative 64 bit pub const R_X86_64_PC64 = 24; /// 64 bit offset to GOT pub const R_X86_64_GOTOFF64 = 25; /// 32 bit signed pc relative offset to GOT pub const R_X86_64_GOTPC32 = 26; /// 64 bit GOT entry offset pub const R_X86_64_GOT64 = 27; /// 64 bit PC relative offset to GOT entry pub const R_X86_64_GOTPCREL64 = 28; /// 64 bit PC relative offset to GOT pub const R_X86_64_GOTPC64 = 29; /// Like GOT64, says PLT entry needed pub const R_X86_64_GOTPLT64 = 30; /// 64-bit GOT relative offset to PLT entry pub const R_X86_64_PLTOFF64 = 31; /// Size of symbol plus 32-bit addend pub const R_X86_64_SIZE32 = 32; /// Size of symbol plus 64-bit addend pub const R_X86_64_SIZE64 = 33; /// GOT offset for TLS descriptor pub const R_X86_64_GOTPC32_TLSDESC = 34; /// Marker for call through TLS descriptor pub const R_X86_64_TLSDESC_CALL = 35; /// TLS descriptor pub const R_X86_64_TLSDESC = 36; /// Adjust indirectly by program base pub const R_X86_64_IRELATIVE = 37; /// 64-bit adjust by program base pub const R_X86_64_RELATIVE64 = 38; /// 39 Reserved was R_X86_64_PC32_BND /// 40 Reserved was R_X86_64_PLT32_BND /// Load from 32 bit signed pc relative offset to GOT entry without REX prefix, relaxable pub const R_X86_64_GOTPCRELX = 41; /// Load from 32 bit signed PC relative offset to GOT entry with REX prefix, relaxable pub const R_X86_64_REX_GOTPCRELX = 42; pub const R_X86_64_NUM = 43; pub const STV = enum(u2) { DEFAULT = 0, INTERNAL = 1, HIDDEN = 2, PROTECTED = 3, }; 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Generated by zstd-live on 2025-08-12 12:37:58 UTC. |