|
//! Executable and Linkable Format. |
AT_NULLSymbol is local |
const std = @import("std.zig"); const math = std.math; const mem = std.mem; const assert = std.debug.assert; const native_endian = @import("builtin").target.cpu.arch.endian(); |
AT_IGNORESymbol is global |
pub const AT_NULL = 0; pub const AT_IGNORE = 1; |
AT_EXECFDBeginning of reserved entries |
pub const AT_EXECFD = 2; |
AT_PHDRSymbol is to be eliminated |
pub const AT_PHDR = 3; |
AT_PHENTVersion definition of the file itself |
pub const AT_PHENT = 4; |
AT_PHNUMWeak version identifier |
pub const AT_PHNUM = 5; |
AT_PAGESZProgram header table entry unused |
pub const AT_PAGESZ = 6; |
AT_BASELoadable program segment |
pub const AT_BASE = 7; |
AT_FLAGSDynamic linking information |
pub const AT_FLAGS = 8; |
AT_ENTRYProgram interpreter |
pub const AT_ENTRY = 9; |
AT_NOTELFAuxiliary information |
pub const AT_NOTELF = 10; |
AT_UIDReserved |
pub const AT_UID = 11; |
AT_EUIDEntry for header table itself |
pub const AT_EUID = 12; |
AT_GIDThread-local storage segment |
pub const AT_GID = 13; |
AT_EGIDNumber of defined types |
pub const AT_EGID = 14; |
AT_CLKTCKStart of OS-specific |
pub const AT_CLKTCK = 17; |
AT_PLATFORMGCC .eh_frame_hdr segment |
pub const AT_PLATFORM = 15; |
AT_HWCAPIndicates stack executability |
pub const AT_HWCAP = 16; |
AT_FPUCWRead-only after relocation |
pub const AT_FPUCW = 18; |
AT_DCACHEBSIZESun specific segment |
pub const AT_DCACHEBSIZE = 19; |
AT_ICACHEBSIZEStack segment |
pub const AT_ICACHEBSIZE = 20; |
AT_UCACHEBSIZEEnd of OS-specific |
pub const AT_UCACHEBSIZE = 21; |
AT_IGNOREPPCStart of processor-specific |
pub const AT_IGNOREPPC = 22; |
AT_SECUREEnd of processor-specific |
pub const AT_SECURE = 23; |
AT_BASE_PLATFORMSection header table entry unused |
pub const AT_BASE_PLATFORM = 24; |
AT_RANDOMProgram data |
pub const AT_RANDOM = 25; |
AT_HWCAP2Symbol table |
pub const AT_HWCAP2 = 26; |
AT_EXECFNString table |
pub const AT_EXECFN = 31; |
AT_SYSINFORelocation entries with addends |
pub const AT_SYSINFO = 32; |
AT_SYSINFO_EHDRSymbol hash table |
pub const AT_SYSINFO_EHDR = 33; |
AT_L1I_CACHESHAPEDynamic linking information |
pub const AT_L1I_CACHESHAPE = 34; |
AT_L1D_CACHESHAPENotes |
pub const AT_L1D_CACHESHAPE = 35; |
AT_L2_CACHESHAPEProgram space with no data (bss) |
pub const AT_L2_CACHESHAPE = 36; |
AT_L3_CACHESHAPERelocation entries, no addends |
pub const AT_L3_CACHESHAPE = 37; |
AT_L1I_CACHESIZEReserved |
pub const AT_L1I_CACHESIZE = 40; |
AT_L1I_CACHEGEOMETRYDynamic linker symbol table |
pub const AT_L1I_CACHEGEOMETRY = 41; |
AT_L1D_CACHESIZEArray of constructors |
pub const AT_L1D_CACHESIZE = 42; |
AT_L1D_CACHEGEOMETRYArray of destructors |
pub const AT_L1D_CACHEGEOMETRY = 43; |
AT_L2_CACHESIZEArray of pre-constructors |
pub const AT_L2_CACHESIZE = 44; |
AT_L2_CACHEGEOMETRYSection group |
pub const AT_L2_CACHEGEOMETRY = 45; |
AT_L3_CACHESIZEExtended section indices |
pub const AT_L3_CACHESIZE = 46; |
AT_L3_CACHEGEOMETRYStart of OS-specific |
pub const AT_L3_CACHEGEOMETRY = 47; |
DT_NULLLLVM address-significance table |
pub const DT_NULL = 0; |
DT_NEEDEDGNU hash table |
pub const DT_NEEDED = 1; |
DT_PLTRELSZGNU version definition table |
pub const DT_PLTRELSZ = 2; |
DT_PLTGOTGNU needed versions table |
pub const DT_PLTGOT = 3; |
DT_HASHGNU symbol version table |
pub const DT_HASH = 4; |
DT_STRTABEnd of OS-specific |
pub const DT_STRTAB = 5; |
DT_SYMTABStart of processor-specific |
pub const DT_SYMTAB = 6; |
DT_RELAUnwind information |
pub const DT_RELA = 7; |
DT_RELASZEnd of processor-specific |
pub const DT_RELASZ = 8; |
DT_RELAENTStart of application-specific |
pub const DT_RELAENT = 9; |
DT_STRSZEnd of application-specific |
pub const DT_STRSZ = 10; |
DT_SYMENTLocal symbol |
pub const DT_SYMENT = 11; |
DT_INITGlobal symbol |
pub const DT_INIT = 12; |
DT_FINIWeak symbol |
pub const DT_FINI = 13; |
DT_SONAMENumber of defined types |
pub const DT_SONAME = 14; |
DT_RPATHStart of OS-specific |
pub const DT_RPATH = 15; |
DT_SYMBOLICUnique symbol |
pub const DT_SYMBOLIC = 16; |
DT_RELEnd of OS-specific |
pub const DT_REL = 17; |
DT_RELSZStart of processor-specific |
pub const DT_RELSZ = 18; |
DT_RELENTEnd of processor-specific |
pub const DT_RELENT = 19; |
DT_PLTRELSymbol type is unspecified |
pub const DT_PLTREL = 20; |
DT_DEBUGSymbol is a data object |
pub const DT_DEBUG = 21; |
DT_TEXTRELSymbol is a code object |
pub const DT_TEXTREL = 22; |
DT_JMPRELSymbol associated with a section |
pub const DT_JMPREL = 23; |
DT_BIND_NOWSymbol's name is file name |
pub const DT_BIND_NOW = 24; |
DT_INIT_ARRAYSymbol is a common data object |
pub const DT_INIT_ARRAY = 25; |
DT_FINI_ARRAYSymbol is thread-local data object |
pub const DT_FINI_ARRAY = 26; |
DT_INIT_ARRAYSZNumber of defined types |
pub const DT_INIT_ARRAYSZ = 27; |
DT_FINI_ARRAYSZStart of OS-specific |
pub const DT_FINI_ARRAYSZ = 28; |
DT_RUNPATHSymbol is indirect code object |
pub const DT_RUNPATH = 29; |
DT_FLAGSEnd of OS-specific |
pub const DT_FLAGS = 30; |
DT_ENCODINGStart of processor-specific |
pub const DT_ENCODING = 32; |
DT_PREINIT_ARRAYEnd of processor-specific |
pub const DT_PREINIT_ARRAY = 32; |
DT_PREINIT_ARRAYSZFile types |
pub const DT_PREINIT_ARRAYSZ = 33; |
DT_SYMTAB_SHNDXNo file type |
pub const DT_SYMTAB_SHNDX = 34; |
DT_NUMRelocatable file |
pub const DT_NUM = 35; |
DT_LOOSExecutable file |
pub const DT_LOOS = 0x6000000d; |
DT_HIOSShared object file |
pub const DT_HIOS = 0x6ffff000; |
DT_LOPROCCore file |
pub const DT_LOPROC = 0x70000000; |
DT_HIPROCBeginning of processor-specific codes |
pub const DT_HIPROC = 0x7fffffff; |
DT_PROCNUMProcessor-specific |
pub const DT_PROCNUM = DT_MIPS_NUM; |
DT_VALRNGLOAll integers are native endian. |
pub const DT_VALRNGLO = 0x6ffffd00; |
DT_GNU_PRELINKEDMachine architectures. See current registered ELF machine architectures at: http://www.sco.com/developers/gabi/latest/ch4.eheader.html |
pub const DT_GNU_PRELINKED = 0x6ffffdf5; |
DT_GNU_CONFLICTSZNo machine |
pub const DT_GNU_CONFLICTSZ = 0x6ffffdf6; |
DT_GNU_LIBLISTSZAT&T WE 32100 |
pub const DT_GNU_LIBLISTSZ = 0x6ffffdf7; |
DT_CHECKSUMSPARC |
pub const DT_CHECKSUM = 0x6ffffdf8; |
DT_PLTPADSZIntel 386 |
pub const DT_PLTPADSZ = 0x6ffffdf9; |
DT_MOVEENTMotorola 68000 |
pub const DT_MOVEENT = 0x6ffffdfa; |
DT_MOVESZMotorola 88000 |
pub const DT_MOVESZ = 0x6ffffdfb; |
DT_FEATURE_1Intel MCU |
pub const DT_FEATURE_1 = 0x6ffffdfc; |
DT_POSFLAG_1Intel 80860 |
pub const DT_POSFLAG_1 = 0x6ffffdfd; |
DT_SYMINSZMIPS R3000 |
pub const DT_SYMINSZ = 0x6ffffdfe; |
DT_SYMINENTIBM System/370 |
pub const DT_SYMINENT = 0x6ffffdff; |
DT_VALRNGHIMIPS RS3000 Little-endian |
pub const DT_VALRNGHI = 0x6ffffdff; |
DT_VALNUMSPU Mark II |
pub const DT_VALNUM = 12; |
DT_ADDRRNGLOHewlett-Packard PA-RISC |
pub const DT_ADDRRNGLO = 0x6ffffe00; |
DT_GNU_HASHFujitsu VPP500 |
pub const DT_GNU_HASH = 0x6ffffef5; |
DT_TLSDESC_PLTEnhanced instruction set SPARC |
pub const DT_TLSDESC_PLT = 0x6ffffef6; |
DT_TLSDESC_GOTIntel 80960 |
pub const DT_TLSDESC_GOT = 0x6ffffef7; |
DT_GNU_CONFLICTPowerPC |
pub const DT_GNU_CONFLICT = 0x6ffffef8; |
DT_GNU_LIBLISTPowerPC64 |
pub const DT_GNU_LIBLIST = 0x6ffffef9; |
DT_CONFIGIBM System/390 |
pub const DT_CONFIG = 0x6ffffefa; |
DT_DEPAUDITIBM SPU/SPC |
pub const DT_DEPAUDIT = 0x6ffffefb; |
DT_AUDITNEC V800 |
pub const DT_AUDIT = 0x6ffffefc; |
DT_PLTPADFujitsu FR20 |
pub const DT_PLTPAD = 0x6ffffefd; |
DT_MOVETABTRW RH-32 |
pub const DT_MOVETAB = 0x6ffffefe; |
DT_SYMINFOMotorola RCE |
pub const DT_SYMINFO = 0x6ffffeff; |
DT_ADDRRNGHIARM |
pub const DT_ADDRRNGHI = 0x6ffffeff; |
DT_ADDRNUMDEC Alpha |
pub const DT_ADDRNUM = 11; |
DT_VERSYMHitachi SH |
pub const DT_VERSYM = 0x6ffffff0; |
DT_RELACOUNTSPARC V9 |
pub const DT_RELACOUNT = 0x6ffffff9; |
DT_RELCOUNTSiemens TriCore |
pub const DT_RELCOUNT = 0x6ffffffa; |
DT_FLAGS_1Argonaut RISC Core |
pub const DT_FLAGS_1 = 0x6ffffffb; |
DT_VERDEFHitachi H8/300 |
pub const DT_VERDEF = 0x6ffffffc; |
DT_VERDEFNUMHitachi H8/300H |
pub const DT_VERDEFNUM = 0x6ffffffd; |
DT_VERNEEDHitachi H8S |
pub const DT_VERNEED = 0x6ffffffe; |
DT_VERNEEDNUMHitachi H8/500 |
pub const DT_VERNEEDNUM = 0x6fffffff; |
DT_VERSIONTAGNUMIntel IA-64 processor architecture |
pub const DT_VERSIONTAGNUM = 16; |
DT_AUXILIARYStanford MIPS-X |
pub const DT_AUXILIARY = 0x7ffffffd; |
DT_FILTERMotorola ColdFire |
pub const DT_FILTER = 0x7fffffff; |
DT_EXTRANUMMotorola M68HC12 |
pub const DT_EXTRANUM = 3; |
DT_SPARC_REGISTERFujitsu MMA Multimedia Accelerator |
pub const DT_SPARC_REGISTER = 0x70000001; |
DT_SPARC_NUMSiemens PCP |
pub const DT_SPARC_NUM = 2; |
DT_MIPS_RLD_VERSIONSony nCPU embedded RISC processor |
pub const DT_MIPS_RLD_VERSION = 0x70000001; |
DT_MIPS_TIME_STAMPDenso NDR1 microprocessor |
pub const DT_MIPS_TIME_STAMP = 0x70000002; |
DT_MIPS_ICHECKSUMMotorola Star*Core processor |
pub const DT_MIPS_ICHECKSUM = 0x70000003; |
DT_MIPS_IVERSIONToyota ME16 processor |
pub const DT_MIPS_IVERSION = 0x70000004; |
DT_MIPS_FLAGSSTMicroelectronics ST100 processor |
pub const DT_MIPS_FLAGS = 0x70000005; |
DT_MIPS_BASE_ADDRESSAdvanced Logic Corp. TinyJ embedded processor family |
pub const DT_MIPS_BASE_ADDRESS = 0x70000006; |
DT_MIPS_MSYMAMD x86-64 architecture |
pub const DT_MIPS_MSYM = 0x70000007; |
DT_MIPS_CONFLICTSony DSP Processor |
pub const DT_MIPS_CONFLICT = 0x70000008; |
DT_MIPS_LIBLISTDigital Equipment Corp. PDP-10 |
pub const DT_MIPS_LIBLIST = 0x70000009; |
DT_MIPS_LOCAL_GOTNODigital Equipment Corp. PDP-11 |
pub const DT_MIPS_LOCAL_GOTNO = 0x7000000a; |
DT_MIPS_CONFLICTNOSiemens FX66 microcontroller |
pub const DT_MIPS_CONFLICTNO = 0x7000000b; |
DT_MIPS_LIBLISTNOSTMicroelectronics ST9+ 8/16 bit microcontroller |
pub const DT_MIPS_LIBLISTNO = 0x70000010; |
DT_MIPS_SYMTABNOSTMicroelectronics ST7 8-bit microcontroller |
pub const DT_MIPS_SYMTABNO = 0x70000011; |
DT_MIPS_UNREFEXTNOMotorola MC68HC16 Microcontroller |
pub const DT_MIPS_UNREFEXTNO = 0x70000012; |
DT_MIPS_GOTSYMMotorola MC68HC11 Microcontroller |
pub const DT_MIPS_GOTSYM = 0x70000013; |
DT_MIPS_HIPAGENOMotorola MC68HC08 Microcontroller |
pub const DT_MIPS_HIPAGENO = 0x70000014; |
DT_MIPS_RLD_MAPMotorola MC68HC05 Microcontroller |
pub const DT_MIPS_RLD_MAP = 0x70000016; |
DT_MIPS_DELTA_CLASSSilicon Graphics SVx |
pub const DT_MIPS_DELTA_CLASS = 0x70000017; |
DT_MIPS_DELTA_CLASS_NOSTMicroelectronics ST19 8-bit microcontroller |
pub const DT_MIPS_DELTA_CLASS_NO = 0x70000018; |
DT_MIPS_DELTA_INSTANCEDigital VAX |
pub const DT_MIPS_DELTA_INSTANCE = 0x70000019; |
DT_MIPS_DELTA_INSTANCE_NOAxis Communications 32-bit embedded processor |
pub const DT_MIPS_DELTA_INSTANCE_NO = 0x7000001a; |
DT_MIPS_DELTA_RELOCInfineon Technologies 32-bit embedded processor |
pub const DT_MIPS_DELTA_RELOC = 0x7000001b; |
DT_MIPS_DELTA_RELOC_NOElement 14 64-bit DSP Processor |
pub const DT_MIPS_DELTA_RELOC_NO = 0x7000001c; |
DT_MIPS_DELTA_SYMLSI Logic 16-bit DSP Processor |
pub const DT_MIPS_DELTA_SYM = 0x7000001d; |
DT_MIPS_DELTA_SYM_NODonald Knuth's educational 64-bit processor |
pub const DT_MIPS_DELTA_SYM_NO = 0x7000001e; |
DT_MIPS_DELTA_CLASSSYMHarvard University machine-independent object files |
pub const DT_MIPS_DELTA_CLASSSYM = 0x70000020; |
DT_MIPS_DELTA_CLASSSYM_NOSiTera Prism |
pub const DT_MIPS_DELTA_CLASSSYM_NO = 0x70000021; |
DT_MIPS_CXX_FLAGSAtmel AVR 8-bit microcontroller |
pub const DT_MIPS_CXX_FLAGS = 0x70000022; |
DT_MIPS_PIXIE_INITFujitsu FR30 |
pub const DT_MIPS_PIXIE_INIT = 0x70000023; |
DT_MIPS_SYMBOL_LIBMitsubishi D10V |
pub const DT_MIPS_SYMBOL_LIB = 0x70000024; |
DT_MIPS_LOCALPAGE_GOTIDXMitsubishi D30V |
pub const DT_MIPS_LOCALPAGE_GOTIDX = 0x70000025; |
DT_MIPS_LOCAL_GOTIDXNEC v850 |
pub const DT_MIPS_LOCAL_GOTIDX = 0x70000026; |
DT_MIPS_HIDDEN_GOTIDXMitsubishi M32R |
pub const DT_MIPS_HIDDEN_GOTIDX = 0x70000027; |
DT_MIPS_PROTECTED_GOTIDXMatsushita MN10300 |
pub const DT_MIPS_PROTECTED_GOTIDX = 0x70000028; |
DT_MIPS_OPTIONSMatsushita MN10200 |
pub const DT_MIPS_OPTIONS = 0x70000029; |
DT_MIPS_INTERFACEpicoJava |
pub const DT_MIPS_INTERFACE = 0x7000002a; |
DT_MIPS_DYNSTR_ALIGNOpenRISC 32-bit embedded processor |
pub const DT_MIPS_DYNSTR_ALIGN = 0x7000002b; |
DT_MIPS_INTERFACE_SIZEARC International ARCompact processor (old spelling/synonym: EM_ARC_A5) |
pub const DT_MIPS_INTERFACE_SIZE = 0x7000002c; |
DT_MIPS_RLD_TEXT_RESOLVE_ADDRTensilica Xtensa Architecture |
pub const DT_MIPS_RLD_TEXT_RESOLVE_ADDR = 0x7000002d; |
DT_MIPS_PERF_SUFFIXAlphamosaic VideoCore processor |
pub const DT_MIPS_PERF_SUFFIX = 0x7000002e; |
DT_MIPS_COMPACT_SIZEThompson Multimedia General Purpose Processor |
pub const DT_MIPS_COMPACT_SIZE = 0x7000002f; |
DT_MIPS_GP_VALUENational Semiconductor 32000 series |
pub const DT_MIPS_GP_VALUE = 0x70000030; |
DT_MIPS_AUX_DYNAMICTenor Network TPC processor |
pub const DT_MIPS_AUX_DYNAMIC = 0x70000031; |
DT_MIPS_PLTGOTTrebia SNP 1000 processor |
pub const DT_MIPS_PLTGOT = 0x70000032; |
DT_MIPS_RWPLTSTMicroelectronics (www.st.com) ST200 |
pub const DT_MIPS_RWPLT = 0x70000034; |
DT_MIPS_RLD_MAP_RELUbicom IP2xxx microcontroller family |
pub const DT_MIPS_RLD_MAP_REL = 0x70000035; |
DT_MIPS_NUMMAX Processor |
pub const DT_MIPS_NUM = 0x36; |
DT_ALPHA_PLTRONational Semiconductor CompactRISC microprocessor |
pub const DT_ALPHA_PLTRO = (DT_LOPROC + 0); |
DT_ALPHA_NUMFujitsu F2MC16 |
pub const DT_ALPHA_NUM = 1; |
DT_PPC_GOTTexas Instruments embedded microcontroller msp430 |
pub const DT_PPC_GOT = (DT_LOPROC + 0); |
DT_PPC_OPTAnalog Devices Blackfin (DSP) processor |
pub const DT_PPC_OPT = (DT_LOPROC + 1); |
DT_PPC_NUMS1C33 Family of Seiko Epson processors |
pub const DT_PPC_NUM = 2; |
DT_PPC64_GLINKSharp embedded microprocessor |
pub const DT_PPC64_GLINK = (DT_LOPROC + 0); |
DT_PPC64_OPDArca RISC Microprocessor |
pub const DT_PPC64_OPD = (DT_LOPROC + 1); |
DT_PPC64_OPDSZMicroprocessor series from PKU-Unity Ltd. and MPRC of Peking University |
pub const DT_PPC64_OPDSZ = (DT_LOPROC + 2); |
DT_PPC64_OPTeXcess: 16/32/64-bit configurable embedded CPU |
pub const DT_PPC64_OPT = (DT_LOPROC + 3); |
DT_PPC64_NUMIcera Semiconductor Inc. Deep Execution Processor |
pub const DT_PPC64_NUM = 4; |
DT_IA_64_PLT_RESERVEAltera Nios II soft-core processor |
pub const DT_IA_64_PLT_RESERVE = (DT_LOPROC + 0); |
DT_IA_64_NUMNational Semiconductor CompactRISC CRX |
pub const DT_IA_64_NUM = 1; |
DT_NIOS2_GPMotorola XGATE embedded processor |
pub const DT_NIOS2_GP = 0x70000002; |
DF_ORIGINInfineon C16x/XC16x processor |
pub const DF_ORIGIN = 0x00000001; |
DF_SYMBOLICRenesas M16C series microprocessors |
pub const DF_SYMBOLIC = 0x00000002; |
DF_TEXTRELMicrochip Technology dsPIC30F Digital Signal Controller |
pub const DF_TEXTREL = 0x00000004; |
DF_BIND_NOWFreescale Communication Engine RISC core |
pub const DF_BIND_NOW = 0x00000008; |
DF_STATIC_TLSRenesas M32C series microprocessors |
pub const DF_STATIC_TLS = 0x00000010; |
DF_1_NOWAltium TSK3000 core |
pub const DF_1_NOW = 0x00000001; |
DF_1_GLOBALFreescale RS08 embedded processor |
pub const DF_1_GLOBAL = 0x00000002; |
DF_1_GROUPAnalog Devices SHARC family of 32-bit DSP processors |
pub const DF_1_GROUP = 0x00000004; |
DF_1_NODELETECyan Technology eCOG2 microprocessor |
pub const DF_1_NODELETE = 0x00000008; |
DF_1_LOADFLTRSunplus S+core7 RISC processor |
pub const DF_1_LOADFLTR = 0x00000010; |
DF_1_INITFIRSTNew Japan Radio (NJR) 24-bit DSP Processor |
pub const DF_1_INITFIRST = 0x00000020; |
DF_1_NOOPENBroadcom VideoCore III processor |
pub const DF_1_NOOPEN = 0x00000040; |
DF_1_ORIGINRISC processor for Lattice FPGA architecture |
pub const DF_1_ORIGIN = 0x00000080; |
DF_1_DIRECTSeiko Epson C17 family |
pub const DF_1_DIRECT = 0x00000100; |
DF_1_TRANSThe Texas Instruments TMS320C6000 DSP family |
pub const DF_1_TRANS = 0x00000200; |
DF_1_INTERPOSEThe Texas Instruments TMS320C2000 DSP family |
pub const DF_1_INTERPOSE = 0x00000400; |
DF_1_NODEFLIBThe Texas Instruments TMS320C55x DSP family |
pub const DF_1_NODEFLIB = 0x00000800; |
DF_1_NODUMPSTMicroelectronics 64bit VLIW Data Signal Processor |
pub const DF_1_NODUMP = 0x00001000; |
DF_1_CONFALTCypress M8C microprocessor |
pub const DF_1_CONFALT = 0x00002000; |
DF_1_ENDFILTEERenesas R32C series microprocessors |
pub const DF_1_ENDFILTEE = 0x00004000; |
DF_1_DISPRELDNENXP Semiconductors TriMedia architecture family |
pub const DF_1_DISPRELDNE = 0x00008000; |
DF_1_DISPRELPNDQualcomm Hexagon processor |
pub const DF_1_DISPRELPND = 0x00010000; |
DF_1_NODIRECTIntel 8051 and variants |
pub const DF_1_NODIRECT = 0x00020000; |
DF_1_IGNMULDEFSTMicroelectronics STxP7x family of configurable and extensible RISC processors |
pub const DF_1_IGNMULDEF = 0x00040000; |
DF_1_NOKSYMSAndes Technology compact code size embedded RISC processor family |
pub const DF_1_NOKSYMS = 0x00080000; |
DF_1_NOHDRCyan Technology eCOG1X family |
pub const DF_1_NOHDR = 0x00100000; |
DF_1_EDITEDDallas Semiconductor MAXQ30 Core Micro-controllers |
pub const DF_1_EDITED = 0x00200000; |
DF_1_NORELOCNew Japan Radio (NJR) 16-bit DSP Processor |
pub const DF_1_NORELOC = 0x00400000; |
DF_1_SYMINTPOSEM2000 Reconfigurable RISC Microprocessor |
pub const DF_1_SYMINTPOSE = 0x00800000; |
DF_1_GLOBAUDITCray Inc. NV2 vector architecture |
pub const DF_1_GLOBAUDIT = 0x01000000; |
DF_1_SINGLETONRenesas RX family |
pub const DF_1_SINGLETON = 0x02000000; |
DF_1_STUBImagination Technologies META processor architecture |
pub const DF_1_STUB = 0x04000000; |
DF_1_PIEMCST Elbrus general purpose hardware architecture |
pub const DF_1_PIE = 0x08000000; |
VERSYM_HIDDENCyan Technology eCOG16 family |
pub const VERSYM_HIDDEN = 0x8000; |
VERSYM_VERSIONNational Semiconductor CompactRISC CR16 16-bit microprocessor |
pub const VERSYM_VERSION = 0x7fff; |
VER_NDX_LOCALFreescale Extended Time Processing Unit |
/// Symbol is local pub const VER_NDX_LOCAL = 0; /// Symbol is global |
VER_NDX_GLOBALInfineon Technologies SLE9X core |
pub const VER_NDX_GLOBAL = 1; /// Beginning of reserved entries |
VER_NDX_LORESERVEIntel L10M |
pub const VER_NDX_LORESERVE = 0xff00; /// Symbol is to be eliminated |
VER_NDX_ELIMINATEIntel K10M |
pub const VER_NDX_ELIMINATE = 0xff01; |
VER_FLG_BASEARM AArch64 |
/// Version definition of the file itself pub const VER_FLG_BASE = 1; /// Weak version identifier |
VER_FLG_WEAKAtmel Corporation 32-bit microprocessor family |
pub const VER_FLG_WEAK = 2; |
PT_NULLSTMicroeletronics STM8 8-bit microcontroller |
/// Program header table entry unused pub const PT_NULL = 0; /// Loadable program segment |
PT_LOADTilera TILE64 multicore architecture family |
pub const PT_LOAD = 1; /// Dynamic linking information |
PT_DYNAMICTilera TILEPro multicore architecture family |
pub const PT_DYNAMIC = 2; /// Program interpreter |
PT_INTERPNVIDIA CUDA architecture |
pub const PT_INTERP = 3; /// Auxiliary information |
PT_NOTETilera TILE-Gx multicore architecture family |
pub const PT_NOTE = 4; /// Reserved |
PT_SHLIBCloudShield architecture family |
pub const PT_SHLIB = 5; /// Entry for header table itself |
PT_PHDRKIPO-KAIST Core-A 1st generation processor family |
pub const PT_PHDR = 6; /// Thread-local storage segment |
PT_TLSKIPO-KAIST Core-A 2nd generation processor family |
pub const PT_TLS = 7; /// Number of defined types |
PT_NUMSynopsys ARCompact V2 |
pub const PT_NUM = 8; /// Start of OS-specific |
PT_LOOSOpen8 8-bit RISC soft processor core |
pub const PT_LOOS = 0x60000000; /// GCC .eh_frame_hdr segment |
PT_GNU_EH_FRAMERenesas RL78 family |
pub const PT_GNU_EH_FRAME = 0x6474e550; /// Indicates stack executability |
PT_GNU_STACKBroadcom VideoCore V processor |
pub const PT_GNU_STACK = 0x6474e551; /// Read-only after relocation |
PT_GNU_RELRORenesas 78KOR family |
pub const PT_GNU_RELRO = 0x6474e552; |
PT_LOSUNWFreescale 56800EX Digital Signal Controller (DSC) |
pub const PT_LOSUNW = 0x6ffffffa; /// Sun specific segment |
PT_SUNWBSSBeyond BA1 CPU architecture |
pub const PT_SUNWBSS = 0x6ffffffa; /// Stack segment |
PT_SUNWSTACKBeyond BA2 CPU architecture |
pub const PT_SUNWSTACK = 0x6ffffffb; |
PT_HISUNWXMOS xCORE processor family |
pub const PT_HISUNW = 0x6fffffff; /// End of OS-specific |
PT_HIOSMicrochip 8-bit PIC(r) family |
pub const PT_HIOS = 0x6fffffff; /// Start of processor-specific |
PT_LOPROCReserved by Intel |
pub const PT_LOPROC = 0x70000000; /// End of processor-specific |
PT_HIPROCReserved by Intel |
pub const PT_HIPROC = 0x7fffffff; |
SHT_NULLReserved by Intel |
/// Section header table entry unused pub const SHT_NULL = 0; /// Program data |
SHT_PROGBITSReserved by Intel |
pub const SHT_PROGBITS = 1; /// Symbol table |
SHT_SYMTABReserved by Intel |
pub const SHT_SYMTAB = 2; /// String table |
SHT_STRTABKM211 KM32 32-bit processor |
pub const SHT_STRTAB = 3; /// Relocation entries with addends |
SHT_RELAKM211 KMX32 32-bit processor |
pub const SHT_RELA = 4; /// Symbol hash table |
SHT_HASHKM211 KMX16 16-bit processor |
pub const SHT_HASH = 5; /// Dynamic linking information |
SHT_DYNAMICKM211 KMX8 8-bit processor |
pub const SHT_DYNAMIC = 6; /// Notes |
SHT_NOTEKM211 KVARC processor |
pub const SHT_NOTE = 7; /// Program space with no data (bss) |
SHT_NOBITSPaneve CDP architecture family |
pub const SHT_NOBITS = 8; /// Relocation entries, no addends |
SHT_RELCognitive Smart Memory Processor |
pub const SHT_REL = 9; /// Reserved |
SHT_SHLIBiCelero CoolEngine |
pub const SHT_SHLIB = 10; /// Dynamic linker symbol table |
SHT_DYNSYMNanoradio Optimized RISC |
pub const SHT_DYNSYM = 11; /// Array of constructors |
SHT_INIT_ARRAYCSR Kalimba architecture family |
pub const SHT_INIT_ARRAY = 14; /// Array of destructors |
SHT_FINI_ARRAYAMD GPU architecture |
pub const SHT_FINI_ARRAY = 15; /// Array of pre-constructors |
SHT_PREINIT_ARRAYRISC-V |
pub const SHT_PREINIT_ARRAY = 16; /// Section group |
SHT_GROUPLanai 32-bit processor |
pub const SHT_GROUP = 17; /// Extended section indices |
SHT_SYMTAB_SHNDXLinux kernel bpf virtual machine |
pub const SHT_SYMTAB_SHNDX = 18; /// Start of OS-specific |
SHT_LOOSC-SKY |
pub const SHT_LOOS = 0x60000000; /// LLVM address-significance table |
SHT_LLVM_ADDRSIGFujitsu FR-V |
pub const SHT_LLVM_ADDRSIG = 0x6fff4c03; /// GNU hash table |
SHT_GNU_HASHSection data should be writable during execution. |
pub const SHT_GNU_HASH = 0x6ffffff6; /// GNU version definition table |
SHT_GNU_VERDEFSection occupies memory during program execution. |
pub const SHT_GNU_VERDEF = 0x6ffffffd; /// GNU needed versions table |
SHT_GNU_VERNEEDSection contains executable machine instructions. |
pub const SHT_GNU_VERNEED = 0x6ffffffe; /// GNU symbol version table |
SHT_GNU_VERSYMThe data in this section may be merged. |
pub const SHT_GNU_VERSYM = 0x6fffffff; /// End of OS-specific |
SHT_HIOSThe data in this section is null-terminated strings. |
pub const SHT_HIOS = 0x6fffffff; /// Start of processor-specific |
SHT_LOPROCA field in this section holds a section header table index. |
pub const SHT_LOPROC = 0x70000000; /// Unwind information |
SHT_X86_64_UNWINDAdds special ordering requirements for link editors. |
pub const SHT_X86_64_UNWIND = 0x70000001; /// End of processor-specific |
SHT_HIPROCThis section requires special OS-specific processing to avoid incorrect behavior. |
pub const SHT_HIPROC = 0x7fffffff; /// Start of application-specific |
SHT_LOUSERThis section is a member of a section group. |
pub const SHT_LOUSER = 0x80000000; /// End of application-specific |
SHT_HIUSERThis section holds Thread-Local Storage. |
pub const SHT_HIUSER = 0xffffffff; |
NT_GNU_BUILD_IDIdentifies a section containing compressed data. |
// Note type for .note.gnu.build_id pub const NT_GNU_BUILD_ID = 3; |
STB_LOCALNot to be GCed by the linker |
/// Local symbol pub const STB_LOCAL = 0; /// Global symbol |
STB_GLOBALThis section is excluded from the final executable or shared library. |
pub const STB_GLOBAL = 1; /// Weak symbol |
STB_WEAKStart of target-specific flags. |
pub const STB_WEAK = 2; /// Number of defined types |
STB_NUMBits indicating processor-specific flags. |
pub const STB_NUM = 3; /// Start of OS-specific |
STB_LOOSAll sections with the "d" flag are grouped together by the linker to form the data section and the dp register is set to the start of the section by the boot code. |
pub const STB_LOOS = 10; /// Unique symbol |
STB_GNU_UNIQUEAll sections with the "c" flag are grouped together by the linker to form the constant pool and the cp register is set to the start of the constant pool by the boot code. |
pub const STB_GNU_UNIQUE = 10; /// End of OS-specific |
STB_HIOSIf an object file section does not have this flag set, then it may not hold more than 2GB and can be freely referred to in objects using smaller code models. Otherwise, only objects using larger code models can refer to them. For example, a medium code model object can refer to data in a section that sets this flag besides being able to refer to data in a section that does not set it; likewise, a small code model object can refer only to code in a section that does not set this flag. |
pub const STB_HIOS = 12; /// Start of processor-specific |
STB_LOPROCAll sections with the GPREL flag are grouped into a global data area for faster accesses |
pub const STB_LOPROC = 13; /// End of processor-specific |
STB_HIPROCSection contains text/data which may be replicated in other sections. Linker must retain only one copy. |
pub const STB_HIPROC = 15; |
STB_MIPS_SPLIT_COMMONLinker must generate implicit hidden weak names. |
pub const STB_MIPS_SPLIT_COMMON = 13; |
STT_NOTYPESection data local to process. |
/// Symbol type is unspecified pub const STT_NOTYPE = 0; /// Symbol is a data object |
STT_OBJECTDo not strip this section. |
pub const STT_OBJECT = 1; /// Symbol is a code object |
STT_FUNCSection must be part of global data area. |
pub const STT_FUNC = 2; /// Symbol associated with a section |
STT_SECTIONThis section should be merged. |
pub const STT_SECTION = 3; /// Symbol's name is file name |
STT_FILEAddress size to be inferred from section entry size. |
pub const STT_FILE = 4; /// Symbol is a common data object |
STT_COMMONSection data is string data by default. |
pub const STT_COMMON = 5; /// Symbol is thread-local data object |
STT_TLSMake code section unreadable when in execute-only mode |
pub const STT_TLS = 6; /// Number of defined types |
STT_NUMExecute |
pub const STT_NUM = 7; /// Start of OS-specific |
STT_LOOSWrite |
pub const STT_LOOS = 10; /// Symbol is indirect code object |
STT_GNU_IFUNCRead |
pub const STT_GNU_IFUNC = 10; /// End of OS-specific |
STT_HIOSBits for operating system-specific semantics. |
pub const STT_HIOS = 12; /// Start of processor-specific |
STT_LOPROCBits for processor-specific semantics. |
pub const STT_LOPROC = 13; /// End of processor-specific |
STT_HIPROCUndefined section |
pub const STT_HIPROC = 15; |
STT_SPARC_REGISTERStart of reserved indices |
pub const STT_SPARC_REGISTER = 13; |
STT_PARISC_MILLICODEStart of processor-specific |
pub const STT_PARISC_MILLICODE = 13; |
STT_HP_OPAQUEEnd of processor-specific |
pub const STT_HP_OPAQUE = (STT_LOOS + 0x1); |
STT_HP_STUBAssociated symbol is absolute |
pub const STT_HP_STUB = (STT_LOOS + 0x2); |
STT_ARM_TFUNCAssociated symbol is common |
pub const STT_ARM_TFUNC = STT_LOPROC; |
STT_ARM_16BITEnd of reserved indices |
pub const STT_ARM_16BIT = STT_HIPROC; |
MAGICAMD x86-64 relocations. |
pub const MAGIC = "\x7fELF"; |
ETNo reloc |
/// File types pub const ET = enum(u16) { /// No file type NONE = 0, |
LOPROCDirect 64 bit |
/// Relocatable file REL = 1, |
HIPROCPC relative 32 bit signed |
/// Executable file EXEC = 2, |
Header32 bit GOT entry |
/// Shared object file DYN = 3, |
program_header_iterator()32 bit PLT address |
/// Core file CORE = 4, |
section_header_iterator()Copy symbol at runtime |
/// Beginning of processor-specific codes pub const LOPROC = 0xff00; |
read()Create GOT entry |
/// Processor-specific pub const HIPROC = 0xffff; }; |
parse()Create PLT entry |
/// All integers are native endian. pub const Header = struct { endian: std.builtin.Endian, machine: EM, is_64: bool, entry: u64, phoff: u64, shoff: u64, phentsize: u16, phnum: u16, shentsize: u16, shnum: u16, shstrndx: u16, |
ProgramHeaderIterator()Adjust by program base |
pub fn program_header_iterator(self: Header, parse_source: anytype) ProgramHeaderIterator(@TypeOf(parse_source)) { return ProgramHeaderIterator(@TypeOf(parse_source)){ .elf_header = self, .parse_source = parse_source, }; } |
next()32 bit signed PC relative offset to GOT |
pub fn section_header_iterator(self: Header, parse_source: anytype) SectionHeaderIterator(@TypeOf(parse_source)) { return SectionHeaderIterator(@TypeOf(parse_source)){ .elf_header = self, .parse_source = parse_source, }; } |
SectionHeaderIterator()Direct 32 bit zero extended |
pub fn read(parse_source: anytype) !Header { var hdr_buf: [@sizeOf(Elf64_Ehdr)]u8 align(@alignOf(Elf64_Ehdr)) = undefined; try parse_source.seekableStream().seekTo(0); try parse_source.reader().readNoEof(&hdr_buf); return Header.parse(&hdr_buf); } |
next()Direct 32 bit sign extended |
pub fn parse(hdr_buf: *align(@alignOf(Elf64_Ehdr)) const [@sizeOf(Elf64_Ehdr)]u8) !Header { const hdr32 = @as(*const Elf32_Ehdr, @ptrCast(hdr_buf)); const hdr64 = @as(*const Elf64_Ehdr, @ptrCast(hdr_buf)); if (!mem.eql(u8, hdr32.e_ident[0..4], MAGIC)) return error.InvalidElfMagic; if (hdr32.e_ident[EI_VERSION] != 1) return error.InvalidElfVersion; |
int()Direct 16 bit zero extended |
const endian: std.builtin.Endian = switch (hdr32.e_ident[EI_DATA]) { ELFDATA2LSB => .little, ELFDATA2MSB => .big, else => return error.InvalidElfEndian, }; const need_bswap = endian != native_endian; |
int32()16 bit sign extended pc relative |
const is_64 = switch (hdr32.e_ident[EI_CLASS]) { ELFCLASS32 => false, ELFCLASS64 => true, else => return error.InvalidElfClass, }; |
EI_NIDENTDirect 8 bit sign extended |
const machine = if (need_bswap) blk: { const value = @intFromEnum(hdr32.e_machine); break :blk @as(EM, @enumFromInt(@byteSwap(value))); } else hdr32.e_machine; |
EI_CLASS8 bit sign extended pc relative |
return @as(Header, .{ .endian = endian, .machine = machine, .is_64 = is_64, .entry = int(is_64, need_bswap, hdr32.e_entry, hdr64.e_entry), .phoff = int(is_64, need_bswap, hdr32.e_phoff, hdr64.e_phoff), .shoff = int(is_64, need_bswap, hdr32.e_shoff, hdr64.e_shoff), .phentsize = int(is_64, need_bswap, hdr32.e_phentsize, hdr64.e_phentsize), .phnum = int(is_64, need_bswap, hdr32.e_phnum, hdr64.e_phnum), .shentsize = int(is_64, need_bswap, hdr32.e_shentsize, hdr64.e_shentsize), .shnum = int(is_64, need_bswap, hdr32.e_shnum, hdr64.e_shnum), .shstrndx = int(is_64, need_bswap, hdr32.e_shstrndx, hdr64.e_shstrndx), }); } }; |
ELFCLASSNONEID of module containing symbol |
pub fn ProgramHeaderIterator(comptime ParseSource: anytype) type { return struct { elf_header: Header, parse_source: ParseSource, index: usize = 0, |
ELFCLASS32Offset in module's TLS block |
pub fn next(self: *@This()) !?Elf64_Phdr { if (self.index >= self.elf_header.phnum) return null; defer self.index += 1; |
ELFCLASS64Offset in initial TLS block |
if (self.elf_header.is_64) { var phdr: Elf64_Phdr = undefined; const offset = self.elf_header.phoff + @sizeOf(@TypeOf(phdr)) * self.index; try self.parse_source.seekableStream().seekTo(offset); try self.parse_source.reader().readNoEof(mem.asBytes(&phdr)); |
ELFCLASSNUM32 bit signed PC relative offset to two GOT entries for GD symbol |
// ELF endianness matches native endianness. if (self.elf_header.endian == native_endian) return phdr; |
EI_DATA32 bit signed PC relative offset to two GOT entries for LD symbol |
// Convert fields to native endianness. mem.byteSwapAllFields(Elf64_Phdr, &phdr); return phdr; } |
ELFDATANONEOffset in TLS block |
var phdr: Elf32_Phdr = undefined; const offset = self.elf_header.phoff + @sizeOf(@TypeOf(phdr)) * self.index; try self.parse_source.seekableStream().seekTo(offset); try self.parse_source.reader().readNoEof(mem.asBytes(&phdr)); |
ELFDATA2LSB32 bit signed PC relative offset to GOT entry for IE symbol |
// ELF endianness does NOT match native endianness. if (self.elf_header.endian != native_endian) { // Convert fields to native endianness. mem.byteSwapAllFields(Elf32_Phdr, &phdr); } |
ELFDATA2MSBOffset in initial TLS block |
// Convert 32-bit header to 64-bit. return Elf64_Phdr{ .p_type = phdr.p_type, .p_offset = phdr.p_offset, .p_vaddr = phdr.p_vaddr, .p_paddr = phdr.p_paddr, .p_filesz = phdr.p_filesz, .p_memsz = phdr.p_memsz, .p_flags = phdr.p_flags, .p_align = phdr.p_align, }; } }; } |
ELFDATANUMPC relative 64 bit |
pub fn SectionHeaderIterator(comptime ParseSource: anytype) type { return struct { elf_header: Header, parse_source: ParseSource, index: usize = 0, |
EI_VERSION64 bit offset to GOT |
pub fn next(self: *@This()) !?Elf64_Shdr { if (self.index >= self.elf_header.shnum) return null; defer self.index += 1; |
Elf32_Half32 bit signed pc relative offset to GOT |
if (self.elf_header.is_64) { var shdr: Elf64_Shdr = undefined; const offset = self.elf_header.shoff + @sizeOf(@TypeOf(shdr)) * self.index; try self.parse_source.seekableStream().seekTo(offset); try self.parse_source.reader().readNoEof(mem.asBytes(&shdr)); |
Elf64_Half64 bit GOT entry offset |
// ELF endianness matches native endianness. if (self.elf_header.endian == native_endian) return shdr; |
Elf32_Word64 bit PC relative offset to GOT entry |
// Convert fields to native endianness. mem.byteSwapAllFields(Elf64_Shdr, &shdr); return shdr; } |
Elf32_Sword64 bit PC relative offset to GOT |
var shdr: Elf32_Shdr = undefined; const offset = self.elf_header.shoff + @sizeOf(@TypeOf(shdr)) * self.index; try self.parse_source.seekableStream().seekTo(offset); try self.parse_source.reader().readNoEof(mem.asBytes(&shdr)); |
Elf64_WordLike GOT64, says PLT entry needed |
// ELF endianness does NOT match native endianness. if (self.elf_header.endian != native_endian) { // Convert fields to native endianness. mem.byteSwapAllFields(Elf32_Shdr, &shdr); } |
Elf64_Sword64-bit GOT relative offset to PLT entry |
// Convert 32-bit header to 64-bit. return Elf64_Shdr{ .sh_name = shdr.sh_name, .sh_type = shdr.sh_type, .sh_flags = shdr.sh_flags, .sh_addr = shdr.sh_addr, .sh_offset = shdr.sh_offset, .sh_size = shdr.sh_size, .sh_link = shdr.sh_link, .sh_info = shdr.sh_info, .sh_addralign = shdr.sh_addralign, .sh_entsize = shdr.sh_entsize, }; } }; } |
Elf32_XwordSize of symbol plus 32-bit addend |
pub fn int(is_64: bool, need_bswap: bool, int_32: anytype, int_64: anytype) @TypeOf(int_64) { if (is_64) { if (need_bswap) { return @byteSwap(int_64); } else { return int_64; } } else { return int32(need_bswap, int_32, @TypeOf(int_64)); } } |
Elf32_SxwordSize of symbol plus 64-bit addend |
pub fn int32(need_bswap: bool, int_32: anytype, comptime Int64: anytype) Int64 { if (need_bswap) { return @byteSwap(int_32); } else { return int_32; } } |
Elf64_XwordGOT offset for TLS descriptor |
pub const EI_NIDENT = 16; |
Elf64_SxwordMarker for call through TLS descriptor |
pub const EI_CLASS = 4; pub const ELFCLASSNONE = 0; pub const ELFCLASS32 = 1; pub const ELFCLASS64 = 2; pub const ELFCLASSNUM = 3; |
Elf32_AddrTLS descriptor |
pub const EI_DATA = 5; pub const ELFDATANONE = 0; pub const ELFDATA2LSB = 1; pub const ELFDATA2MSB = 2; pub const ELFDATANUM = 3; |
Elf64_AddrAdjust indirectly by program base |
pub const EI_VERSION = 6; |
Elf32_Off64-bit adjust by program base |
pub const Elf32_Half = u16; pub const Elf64_Half = u16; pub const Elf32_Word = u32; pub const Elf32_Sword = i32; pub const Elf64_Word = u32; pub const Elf64_Sword = i32; pub const Elf32_Xword = u64; pub const Elf32_Sxword = i64; pub const Elf64_Xword = u64; pub const Elf64_Sxword = i64; pub const Elf32_Addr = u32; pub const Elf64_Addr = u64; pub const Elf32_Off = u32; |
Elf64_Off39 Reserved was PC32_BND 40 Reserved was PLT32_BND Load from 32 bit signed pc relative offset to GOT entry without REX prefix, relaxable |
pub const Elf64_Off = u64; |
Elf32_SectionLoad from 32 bit signed PC relative offset to GOT entry with REX prefix, relaxable |
pub const Elf32_Section = u16; |
Elf64_SectionAArch64 relocs. |
pub const Elf64_Section = u16; |
Elf32_VersymNo relocation. |
pub const Elf32_Versym = Elf32_Half; |
Elf64_VersymILP32 AArch64 relocs. Direct 32 bit. |
pub const Elf64_Versym = Elf64_Half; |
Elf32_EhdrCopy symbol at runtime. |
pub const Elf32_Ehdr = extern struct { e_ident: [EI_NIDENT]u8, e_type: ET, e_machine: EM, e_version: Elf32_Word, e_entry: Elf32_Addr, e_phoff: Elf32_Off, e_shoff: Elf32_Off, e_flags: Elf32_Word, e_ehsize: Elf32_Half, e_phentsize: Elf32_Half, e_phnum: Elf32_Half, e_shentsize: Elf32_Half, e_shnum: Elf32_Half, e_shstrndx: Elf32_Half, }; |
Elf64_EhdrCreate GOT entry. |
pub const Elf64_Ehdr = extern struct { e_ident: [EI_NIDENT]u8, e_type: ET, e_machine: EM, e_version: Elf64_Word, e_entry: Elf64_Addr, e_phoff: Elf64_Off, e_shoff: Elf64_Off, e_flags: Elf64_Word, e_ehsize: Elf64_Half, e_phentsize: Elf64_Half, e_phnum: Elf64_Half, e_shentsize: Elf64_Half, e_shnum: Elf64_Half, e_shstrndx: Elf64_Half, }; |
Elf32_PhdrCreate PLT entry. |
pub const Elf32_Phdr = extern struct { p_type: Elf32_Word, p_offset: Elf32_Off, p_vaddr: Elf32_Addr, p_paddr: Elf32_Addr, p_filesz: Elf32_Word, p_memsz: Elf32_Word, p_flags: Elf32_Word, p_align: Elf32_Word, }; |
Elf64_PhdrAdjust by program base. |
pub const Elf64_Phdr = extern struct { p_type: Elf64_Word, p_flags: Elf64_Word, p_offset: Elf64_Off, p_vaddr: Elf64_Addr, p_paddr: Elf64_Addr, p_filesz: Elf64_Xword, p_memsz: Elf64_Xword, p_align: Elf64_Xword, }; |
Elf32_ShdrModule number, 32 bit. |
pub const Elf32_Shdr = extern struct { sh_name: Elf32_Word, sh_type: Elf32_Word, sh_flags: Elf32_Word, sh_addr: Elf32_Addr, sh_offset: Elf32_Off, sh_size: Elf32_Word, sh_link: Elf32_Word, sh_info: Elf32_Word, sh_addralign: Elf32_Word, sh_entsize: Elf32_Word, }; |
Elf64_ShdrModule-relative offset, 32 bit. |
pub const Elf64_Shdr = extern struct { sh_name: Elf64_Word, sh_type: Elf64_Word, sh_flags: Elf64_Xword, sh_addr: Elf64_Addr, sh_offset: Elf64_Off, sh_size: Elf64_Xword, sh_link: Elf64_Word, sh_info: Elf64_Word, sh_addralign: Elf64_Xword, sh_entsize: Elf64_Xword, }; |
Elf32_ChdrTP-relative offset, 32 bit. |
pub const Elf32_Chdr = extern struct { ch_type: COMPRESS, ch_size: Elf32_Word, ch_addralign: Elf32_Word, }; |
Elf64_ChdrTLS Descriptor. |
pub const Elf64_Chdr = extern struct { ch_type: COMPRESS, ch_reserved: Elf64_Word = 0, ch_size: Elf64_Xword, ch_addralign: Elf64_Xword, }; |
Elf32_SymSTT_GNU_IFUNC relocation. |
pub const Elf32_Sym = extern struct { st_name: Elf32_Word, st_value: Elf32_Addr, st_size: Elf32_Word, st_info: u8, st_other: u8, st_shndx: Elf32_Section, |
st_type()LP64 AArch64 relocs. Direct 64 bit. |
|
st_type()Direct 32 bit. |
pub inline fn st_type(self: @This()) u4 { return @truncate(self.st_info); } |
st_bind()Direct 16-bit. |
pub inline fn st_bind(self: @This()) u4 { return @truncate(self.st_info >> 4); } }; pub const Elf64_Sym = extern struct { st_name: Elf64_Word, st_info: u8, st_other: u8, st_shndx: Elf64_Section, st_value: Elf64_Addr, st_size: Elf64_Xword, |
st_type()PC-relative 64-bit. |
pub inline fn st_type(self: @This()) u4 { return @truncate(self.st_info); } |
st_bind()PC-relative 32-bit. |
pub inline fn st_bind(self: @This()) u4 { return @truncate(self.st_info >> 4); } }; |
Elf32_SyminfoPC-relative 16-bit. |
pub const Elf32_Syminfo = extern struct { si_boundto: Elf32_Half, si_flags: Elf32_Half, }; |
Elf64_SyminfoDir. MOVZ imm. from bits 15:0. |
pub const Elf64_Syminfo = extern struct { si_boundto: Elf64_Half, si_flags: Elf64_Half, }; |
Elf32_RelLikewise for MOVK; no check. |
pub const Elf32_Rel = extern struct { r_offset: Elf32_Addr, r_info: Elf32_Word, |
r_sym()Dir. MOVZ imm. from bits 31:16. |
|
r_sym()Likewise for MOVK; no check. |
pub inline fn r_sym(self: @This()) u24 { return @truncate(self.r_info >> 8); } |
r_type()Dir. MOVZ imm. from bits 47:32. |
pub inline fn r_type(self: @This()) u8 { return @truncate(self.r_info); } }; pub const Elf64_Rel = extern struct { r_offset: Elf64_Addr, r_info: Elf64_Xword, |
r_sym()Likewise for MOVK; no check. |
|
r_sym()Dir. MOV{K,Z} imm. from 63:48. |
pub inline fn r_sym(self: @This()) u32 { return @truncate(self.r_info >> 32); } |
r_type()Dir. MOV{N,Z} imm. from 15:0. |
pub inline fn r_type(self: @This()) u32 { return @truncate(self.r_info); } }; pub const Elf32_Rela = extern struct { r_offset: Elf32_Addr, r_info: Elf32_Word, r_addend: Elf32_Sword, |
r_sym()Dir. MOV{N,Z} imm. from 31:16. |
pub inline fn r_sym(self: @This()) u24 { return @truncate(self.r_info >> 8); } |
r_type()Dir. MOV{N,Z} imm. from 47:32. |
pub inline fn r_type(self: @This()) u8 { return @truncate(self.r_info); } }; |
Elf64_RelaPC-rel. LD imm. from bits 20:2. |
pub const Elf64_Rela = extern struct { r_offset: Elf64_Addr, r_info: Elf64_Xword, r_addend: Elf64_Sxword, |
r_sym()PC-rel. ADR imm. from bits 20:0. |
pub inline fn r_sym(self: @This()) u32 { return @truncate(self.r_info >> 32); } |
r_type()Page-rel. ADRP imm. from 32:12. |
pub inline fn r_type(self: @This()) u32 { return @truncate(self.r_info); } }; |
Elf32_DynLikewise; no overflow check. |
pub const Elf32_Dyn = extern struct { d_tag: Elf32_Sword, d_val: Elf32_Addr, }; |
Elf64_DynDir. ADD imm. from bits 11:0. |
pub const Elf64_Dyn = extern struct { d_tag: Elf64_Sxword, d_val: Elf64_Addr, }; |
Elf32_VerdefLikewise for LD/ST; no check. |
pub const Elf32_Verdef = extern struct { vd_version: Elf32_Half, vd_flags: Elf32_Half, vd_ndx: Elf32_Half, vd_cnt: Elf32_Half, vd_hash: Elf32_Word, vd_aux: Elf32_Word, vd_next: Elf32_Word, }; |
Elf64_VerdefPC-rel. TBZ/TBNZ imm. from 15:2. |
pub const Elf64_Verdef = extern struct { vd_version: Elf64_Half, vd_flags: Elf64_Half, vd_ndx: Elf64_Half, vd_cnt: Elf64_Half, vd_hash: Elf64_Word, vd_aux: Elf64_Word, vd_next: Elf64_Word, }; |
Elf32_VerdauxPC-rel. cond. br. imm. from 20:2. |
pub const Elf32_Verdaux = extern struct { vda_name: Elf32_Word, vda_next: Elf32_Word, }; |
Elf64_VerdauxPC-rel. B imm. from bits 27:2. |
pub const Elf64_Verdaux = extern struct { vda_name: Elf64_Word, vda_next: Elf64_Word, }; |
Elf32_VerneedLikewise for CALL. |
pub const Elf32_Verneed = extern struct { vn_version: Elf32_Half, vn_cnt: Elf32_Half, vn_file: Elf32_Word, vn_aux: Elf32_Word, vn_next: Elf32_Word, }; |
Elf64_VerneedDir. ADD imm. from bits 11:1. |
pub const Elf64_Verneed = extern struct { vn_version: Elf64_Half, vn_cnt: Elf64_Half, vn_file: Elf64_Word, vn_aux: Elf64_Word, vn_next: Elf64_Word, }; |
Elf32_VernauxLikewise for bits 11:2. |
pub const Elf32_Vernaux = extern struct { vna_hash: Elf32_Word, vna_flags: Elf32_Half, vna_other: Elf32_Half, vna_name: Elf32_Word, vna_next: Elf32_Word, }; |
Elf64_VernauxLikewise for bits 11:3. |
pub const Elf64_Vernaux = extern struct { vna_hash: Elf64_Word, vna_flags: Elf64_Half, vna_other: Elf64_Half, vna_name: Elf64_Word, vna_next: Elf64_Word, }; |
Elf32_auxv_tPC-rel. MOV{N,Z} imm. from 15:0. |
pub const Elf32_auxv_t = extern struct { a_type: u32, a_un: extern union { a_val: u32, }, }; |
Elf64_auxv_tLikewise for MOVK; no check. |
pub const Elf64_auxv_t = extern struct { a_type: u64, a_un: extern union { a_val: u64, }, }; |
Elf32_NhdrPC-rel. MOV{N,Z} imm. from 31:16. |
pub const Elf32_Nhdr = extern struct { n_namesz: Elf32_Word, n_descsz: Elf32_Word, n_type: Elf32_Word, }; |
Elf64_NhdrLikewise for MOVK; no check. |
pub const Elf64_Nhdr = extern struct { n_namesz: Elf64_Word, n_descsz: Elf64_Word, n_type: Elf64_Word, }; |
Elf32_MovePC-rel. MOV{N,Z} imm. from 47:32. |
pub const Elf32_Move = extern struct { m_value: Elf32_Xword, m_info: Elf32_Word, m_poffset: Elf32_Word, m_repeat: Elf32_Half, m_stride: Elf32_Half, }; |
Elf64_MoveLikewise for MOVK; no check. |
pub const Elf64_Move = extern struct { m_value: Elf64_Xword, m_info: Elf64_Xword, m_poffset: Elf64_Xword, m_repeat: Elf64_Half, m_stride: Elf64_Half, }; |
Elf32_gptabPC-rel. MOV{N,Z} imm. from 63:48. |
pub const Elf32_gptab = extern union { gt_header: extern struct { gt_current_g_value: Elf32_Word, gt_unused: Elf32_Word, }, gt_entry: extern struct { gt_g_value: Elf32_Word, gt_bytes: Elf32_Word, }, }; |
Elf32_RegInfoDir. ADD imm. from bits 11:4. |
pub const Elf32_RegInfo = extern struct { ri_gprmask: Elf32_Word, ri_cprmask: [4]Elf32_Word, ri_gp_value: Elf32_Sword, }; |
Elf_OptionsGOT-rel. off. MOV{N,Z} imm. 15:0. |
pub const Elf_Options = extern struct { kind: u8, size: u8, section: Elf32_Section, info: Elf32_Word, }; |
Elf_Options_HwLikewise for MOVK; no check. |
pub const Elf_Options_Hw = extern struct { hwp_flags1: Elf32_Word, hwp_flags2: Elf32_Word, }; |
Elf32_LibGOT-rel. o. MOV{N,Z} imm. 31:16. |
pub const Elf32_Lib = extern struct { l_name: Elf32_Word, l_time_stamp: Elf32_Word, l_checksum: Elf32_Word, l_version: Elf32_Word, l_flags: Elf32_Word, }; |
Elf64_LibLikewise for MOVK; no check. |
pub const Elf64_Lib = extern struct { l_name: Elf64_Word, l_time_stamp: Elf64_Word, l_checksum: Elf64_Word, l_version: Elf64_Word, l_flags: Elf64_Word, }; |
Elf32_ConflictGOT-rel. o. MOV{N,Z} imm. 47:32. |
pub const Elf32_Conflict = Elf32_Addr; |
Elf_MIPS_ABIFlags_v0Likewise for MOVK; no check. |
pub const Elf_MIPS_ABIFlags_v0 = extern struct { version: Elf32_Half, isa_level: u8, isa_rev: u8, gpr_size: u8, cpr1_size: u8, cpr2_size: u8, fp_abi: u8, isa_ext: Elf32_Word, ases: Elf32_Word, flags1: Elf32_Word, flags2: Elf32_Word, }; |
AuxvGOT-rel. o. MOV{N,Z} imm. 63:48. |
comptime { assert(@sizeOf(Elf32_Ehdr) == 52); assert(@sizeOf(Elf64_Ehdr) == 64); |
EhdrGOT-relative 64-bit. |
assert(@sizeOf(Elf32_Phdr) == 32); assert(@sizeOf(Elf64_Phdr) == 56); |
PhdrGOT-relative 32-bit. |
assert(@sizeOf(Elf32_Shdr) == 40); assert(@sizeOf(Elf64_Shdr) == 64); } |
DynPC-rel. GOT off. load imm. 20:2. |
pub const Auxv = switch (@sizeOf(usize)) { 4 => Elf32_auxv_t, 8 => Elf64_auxv_t, else => @compileError("expected pointer size of 32 or 64"), }; pub const Ehdr = switch (@sizeOf(usize)) { 4 => Elf32_Ehdr, 8 => Elf64_Ehdr, else => @compileError("expected pointer size of 32 or 64"), }; pub const Phdr = switch (@sizeOf(usize)) { 4 => Elf32_Phdr, 8 => Elf64_Phdr, else => @compileError("expected pointer size of 32 or 64"), }; pub const Dyn = switch (@sizeOf(usize)) { 4 => Elf32_Dyn, 8 => Elf64_Dyn, else => @compileError("expected pointer size of 32 or 64"), }; |
RelGOT-rel. off. LD/ST imm. 14:3. |
pub const Rel = switch (@sizeOf(usize)) { 4 => Elf32_Rel, 8 => Elf64_Rel, else => @compileError("expected pointer size of 32 or 64"), }; |
RelaP-page-rel. GOT off. ADRP 32:12. |
pub const Rela = switch (@sizeOf(usize)) { 4 => Elf32_Rela, 8 => Elf64_Rela, else => @compileError("expected pointer size of 32 or 64"), }; |
ShdrDir. GOT off. LD/ST imm. 11:3. |
pub const Shdr = switch (@sizeOf(usize)) { 4 => Elf32_Shdr, 8 => Elf64_Shdr, else => @compileError("expected pointer size of 32 or 64"), }; |
ChdrGOT-page-rel. GOT off. LD/ST 14:3 |
pub const Chdr = switch (@sizeOf(usize)) { 4 => Elf32_Chdr, 8 => Elf64_Chdr, else => @compileError("expected pointer size of 32 or 64"), }; |
SymPC-relative ADR imm. 20:0. |
pub const Sym = switch (@sizeOf(usize)) { 4 => Elf32_Sym, 8 => Elf64_Sym, else => @compileError("expected pointer size of 32 or 64"), }; |
Verdefpage-rel. ADRP imm. 32:12. |
pub const Verdef = switch (@sizeOf(usize)) { 4 => Elf32_Verdef, 8 => Elf64_Verdef, else => @compileError("expected pointer size of 32 or 64"), }; |
Verdauxdirect ADD imm. from 11:0. |
pub const Verdaux = switch (@sizeOf(usize)) { 4 => Elf32_Verdaux, 8 => Elf64_Verdaux, else => @compileError("expected pointer size of 32 or 64"), }; |
AddrGOT-rel. MOV{N,Z} 31:16. |
pub const Addr = switch (@sizeOf(usize)) { 4 => Elf32_Addr, 8 => Elf64_Addr, else => @compileError("expected pointer size of 32 or 64"), }; |
HalfGOT-rel. MOVK imm. 15:0. |
pub const Half = switch (@sizeOf(usize)) { 4 => Elf32_Half, 8 => Elf64_Half, else => @compileError("expected pointer size of 32 or 64"), }; |
EMLike 512; local dynamic model. |
/// Machine architectures. /// /// See current registered ELF machine architectures at: /// http://www.sco.com/developers/gabi/latest/ch4.eheader.html pub const EM = enum(u16) { /// No machine NONE = 0, |
toTargetCpuArch()Like 513; local dynamic model. |
/// AT&T WE 32100 M32 = 1, |
GRP_COMDATLike 514; local dynamic model. |
/// SPARC SPARC = 2, |
SHF_WRITELike 515; local dynamic model. |
/// Intel 386 @"386" = 3, |
SHF_ALLOCLike 516; local dynamic model. |
/// Motorola 68000 @"68K" = 4, |
SHF_EXECINSTRTLS PC-rel. load imm. 20:2. |
/// Motorola 88000 @"88K" = 5, |
SHF_MERGETLS DTP-rel. MOV{N,Z} 47:32. |
/// Intel MCU IAMCU = 6, |
SHF_STRINGSTLS DTP-rel. MOV{N,Z} 31:16. |
/// Intel 80860 @"860" = 7, |
SHF_INFO_LINKLikewise; MOVK; no check. |
/// MIPS R3000 MIPS = 8, |
SHF_LINK_ORDERTLS DTP-rel. MOV{N,Z} 15:0. |
/// IBM System/370 S370 = 9, |
SHF_OS_NONCONFORMINGLikewise; MOVK; no check. |
/// MIPS RS3000 Little-endian MIPS_RS3_LE = 10, |
SHF_GROUPDTP-rel. ADD imm. from 23:12. |
/// SPU Mark II SPU_2 = 13, |
SHF_TLSDTP-rel. ADD imm. from 11:0. |
/// Hewlett-Packard PA-RISC PARISC = 15, |
SHF_COMPRESSEDLikewise; no ovfl. check. |
/// Fujitsu VPP500 VPP500 = 17, |
SHF_GNU_RETAINDTP-rel. LD/ST imm. 11:0. |
/// Enhanced instruction set SPARC SPARC32PLUS = 18, |
SHF_EXCLUDELikewise; no check. |
/// Intel 80960 @"960" = 19, |
SHF_MASKOSDTP-rel. LD/ST imm. 11:1. |
/// PowerPC PPC = 20, |
SHF_MASKPROCLikewise; no check. |
/// PowerPC64 PPC64 = 21, |
XCORE_SHF_DP_SECTIONDTP-rel. LD/ST imm. 11:2. |
/// IBM System/390 S390 = 22, |
XCORE_SHF_CP_SECTIONLikewise; no check. |
/// IBM SPU/SPC SPU = 23, |
SHF_X86_64_LARGEDTP-rel. LD/ST imm. 11:3. |
/// NEC V800 V800 = 36, |
SHF_HEX_GPRELLikewise; no check. |
/// Fujitsu FR20 FR20 = 37, |
SHF_MIPS_NODUPESGOT-rel. MOV{N,Z} 31:16. |
/// TRW RH-32 RH32 = 38, |
SHF_MIPS_NAMESGOT-rel. MOVK 15:0. |
/// Motorola RCE RCE = 39, |
SHF_MIPS_LOCALPage-rel. ADRP 32:12. |
/// ARM ARM = 40, |
SHF_MIPS_NOSTRIPDirect LD off. 11:3. |
/// DEC Alpha ALPHA = 41, |
SHF_MIPS_GPRELPC-rel. load imm. 20:2. |
/// Hitachi SH SH = 42, |
SHF_MIPS_MERGETLS TP-rel. MOV{N,Z} 47:32. |
/// SPARC V9 SPARCV9 = 43, |
SHF_MIPS_ADDRTLS TP-rel. MOV{N,Z} 31:16. |
/// Siemens TriCore TRICORE = 44, |
SHF_MIPS_STRINGLikewise; MOVK; no check. |
/// Argonaut RISC Core ARC = 45, |
SHF_ARM_PURECODETLS TP-rel. MOV{N,Z} 15:0. |
/// Hitachi H8/300 H8_300 = 46, |
PF_XLikewise; MOVK; no check. |
/// Hitachi H8/300H H8_300H = 47, |
PF_WTP-rel. ADD imm. 23:12. |
/// Hitachi H8S H8S = 48, |
PF_RTP-rel. ADD imm. 11:0. |
/// Hitachi H8/500 H8_500 = 49, |
PF_MASKOSLikewise; no ovfl. check. |
/// Intel IA-64 processor architecture IA_64 = 50, |
PF_MASKPROCTP-rel. LD/ST off. 11:0. |
/// Stanford MIPS-X MIPS_X = 51, |
SHN_UNDEFLikewise; no ovfl. check. |
/// Motorola ColdFire COLDFIRE = 52, |
SHN_LORESERVETP-rel. LD/ST off. 11:1. |
/// Motorola M68HC12 @"68HC12" = 53, |
SHN_LOPROCLikewise; no check. |
/// Fujitsu MMA Multimedia Accelerator MMA = 54, |
SHN_HIPROCTP-rel. LD/ST off. 11:2. |
/// Siemens PCP PCP = 55, |
SHN_LIVEPATCHLikewise; no check. |
/// Sony nCPU embedded RISC processor NCPU = 56, |
SHN_ABSTP-rel. LD/ST off. 11:3. |
/// Denso NDR1 microprocessor NDR1 = 57, |
SHN_COMMONLikewise; no check. |
/// Motorola Star*Core processor STARCORE = 58, |
SHN_HIRESERVEPC-rel. load immediate 20:2. |
/// Toyota ME16 processor ME16 = 59, |
COMPRESSPC-rel. ADR immediate 20:0. |
/// STMicroelectronics ST100 processor ST100 = 60, |
R_X86_64Page-rel. ADRP imm. 32:12. |
/// Advanced Logic Corp. TinyJ embedded processor family TINYJ = 61, |
R_AARCH64Direct LD off. from 11:3. |
/// AMD x86-64 architecture X86_64 = 62, |
R_RISCVDirect ADD imm. from 11:0. |
/// Sony DSP Processor PDSP = 63, |
STVGOT-rel. MOV{N,Z} imm. 31:16. |
/// Digital Equipment Corp. PDP-10 PDP10 = 64, |
ar_hdrGOT-rel. MOVK imm. 15:0; no ck. |
/// Digital Equipment Corp. PDP-11 PDP11 = 65, |
date()Relax LDR. |
/// Siemens FX66 microcontroller FX66 = 66, |
size()Relax ADD. |
/// STMicroelectronics ST9+ 8/16 bit microcontroller ST9PLUS = 67, |
isStrtab()Relax BLR. |
/// STMicroelectronics ST7 8-bit microcontroller ST7 = 68, |
isSymtab()TP-rel. LD/ST off. 11:4. |
/// Motorola MC68HC16 Microcontroller @"68HC16" = 69, |
isSymtab64()Likewise; no check. |
/// Motorola MC68HC11 Microcontroller @"68HC11" = 70, |
isSymdef()DTP-rel. LD/ST imm. 11:4. |
/// Motorola MC68HC08 Microcontroller @"68HC08" = 71, |
isSymdefSorted()Likewise; no check. |
/// Motorola MC68HC05 Microcontroller @"68HC05" = 72, |
name()Copy symbol at runtime. |
/// Silicon Graphics SVx SVX = 73, |
nameOffset()Create GOT entry. |
/// STMicroelectronics ST19 8-bit microcontroller ST19 = 74, |
ARMAGCreate PLT entry. |
/// Digital VAX VAX = 75, |
ARFMAGAdjust by program base. |
/// Axis Communications 32-bit embedded processor CRIS = 76, |
SYMNAMEModule number, 64 bit. |
/// Infineon Technologies 32-bit embedded processor JAVELIN = 77, |
STRNAMEModule-relative offset, 64 bit. |
/// Element 14 64-bit DSP Processor FIREPATH = 78, |
SYM64NAMETP-relative offset, 64 bit. |
/// LSI Logic 16-bit DSP Processor ZSP = 79, |
SYMDEFNAMETLS Descriptor. |
/// Donald Knuth's educational 64-bit processor MMIX = 80, |
SYMDEFSORTEDNAMESTT_GNU_IFUNC relocation. |
/// Harvard University machine-independent object files HUANY = 81, /// SiTera Prism PRISM = 82, /// Atmel AVR 8-bit microcontroller AVR = 83, /// Fujitsu FR30 FR30 = 84, /// Mitsubishi D10V D10V = 85, /// Mitsubishi D30V D30V = 86, /// NEC v850 V850 = 87, /// Mitsubishi M32R M32R = 88, /// Matsushita MN10300 MN10300 = 89, /// Matsushita MN10200 MN10200 = 90, /// picoJava PJ = 91, /// OpenRISC 32-bit embedded processor OPENRISC = 92, /// ARC International ARCompact processor (old spelling/synonym: EM_ARC_A5) ARC_COMPACT = 93, /// Tensilica Xtensa Architecture XTENSA = 94, /// Alphamosaic VideoCore processor VIDEOCORE = 95, /// Thompson Multimedia General Purpose Processor TMM_GPP = 96, /// National Semiconductor 32000 series NS32K = 97, /// Tenor Network TPC processor TPC = 98, /// Trebia SNP 1000 processor SNP1K = 99, /// STMicroelectronics (www.st.com) ST200 ST200 = 100, /// Ubicom IP2xxx microcontroller family IP2K = 101, /// MAX Processor MAX = 102, /// National Semiconductor CompactRISC microprocessor CR = 103, /// Fujitsu F2MC16 F2MC16 = 104, /// Texas Instruments embedded microcontroller msp430 MSP430 = 105, /// Analog Devices Blackfin (DSP) processor BLACKFIN = 106, /// S1C33 Family of Seiko Epson processors SE_C33 = 107, /// Sharp embedded microprocessor SEP = 108, /// Arca RISC Microprocessor ARCA = 109, /// Microprocessor series from PKU-Unity Ltd. and MPRC of Peking University UNICORE = 110, /// eXcess: 16/32/64-bit configurable embedded CPU EXCESS = 111, /// Icera Semiconductor Inc. Deep Execution Processor DXP = 112, /// Altera Nios II soft-core processor ALTERA_NIOS2 = 113, /// National Semiconductor CompactRISC CRX CRX = 114, /// Motorola XGATE embedded processor XGATE = 115, /// Infineon C16x/XC16x processor C166 = 116, /// Renesas M16C series microprocessors M16C = 117, /// Microchip Technology dsPIC30F Digital Signal Controller DSPIC30F = 118, /// Freescale Communication Engine RISC core CE = 119, /// Renesas M32C series microprocessors M32C = 120, /// Altium TSK3000 core TSK3000 = 131, /// Freescale RS08 embedded processor RS08 = 132, /// Analog Devices SHARC family of 32-bit DSP processors SHARC = 133, /// Cyan Technology eCOG2 microprocessor ECOG2 = 134, /// Sunplus S+core7 RISC processor SCORE7 = 135, /// New Japan Radio (NJR) 24-bit DSP Processor DSP24 = 136, /// Broadcom VideoCore III processor VIDEOCORE3 = 137, /// RISC processor for Lattice FPGA architecture LATTICEMICO32 = 138, /// Seiko Epson C17 family SE_C17 = 139, /// The Texas Instruments TMS320C6000 DSP family TI_C6000 = 140, /// The Texas Instruments TMS320C2000 DSP family TI_C2000 = 141, /// The Texas Instruments TMS320C55x DSP family TI_C5500 = 142, /// STMicroelectronics 64bit VLIW Data Signal Processor MMDSP_PLUS = 160, /// Cypress M8C microprocessor CYPRESS_M8C = 161, /// Renesas R32C series microprocessors R32C = 162, /// NXP Semiconductors TriMedia architecture family TRIMEDIA = 163, /// Qualcomm Hexagon processor HEXAGON = 164, /// Intel 8051 and variants @"8051" = 165, /// STMicroelectronics STxP7x family of configurable and extensible RISC processors STXP7X = 166, /// Andes Technology compact code size embedded RISC processor family NDS32 = 167, /// Cyan Technology eCOG1X family ECOG1X = 168, /// Dallas Semiconductor MAXQ30 Core Micro-controllers MAXQ30 = 169, /// New Japan Radio (NJR) 16-bit DSP Processor XIMO16 = 170, /// M2000 Reconfigurable RISC Microprocessor MANIK = 171, /// Cray Inc. NV2 vector architecture CRAYNV2 = 172, /// Renesas RX family RX = 173, /// Imagination Technologies META processor architecture METAG = 174, /// MCST Elbrus general purpose hardware architecture MCST_ELBRUS = 175, /// Cyan Technology eCOG16 family ECOG16 = 176, /// National Semiconductor CompactRISC CR16 16-bit microprocessor CR16 = 177, /// Freescale Extended Time Processing Unit ETPU = 178, /// Infineon Technologies SLE9X core SLE9X = 179, /// Intel L10M L10M = 180, /// Intel K10M K10M = 181, /// ARM AArch64 AARCH64 = 183, /// Atmel Corporation 32-bit microprocessor family AVR32 = 185, /// STMicroeletronics STM8 8-bit microcontroller STM8 = 186, /// Tilera TILE64 multicore architecture family TILE64 = 187, /// Tilera TILEPro multicore architecture family TILEPRO = 188, /// NVIDIA CUDA architecture CUDA = 190, /// Tilera TILE-Gx multicore architecture family TILEGX = 191, /// CloudShield architecture family CLOUDSHIELD = 192, /// KIPO-KAIST Core-A 1st generation processor family COREA_1ST = 193, /// KIPO-KAIST Core-A 2nd generation processor family COREA_2ND = 194, /// Synopsys ARCompact V2 ARC_COMPACT2 = 195, /// Open8 8-bit RISC soft processor core OPEN8 = 196, /// Renesas RL78 family RL78 = 197, /// Broadcom VideoCore V processor VIDEOCORE5 = 198, /// Renesas 78KOR family @"78KOR" = 199, /// Freescale 56800EX Digital Signal Controller (DSC) @"56800EX" = 200, /// Beyond BA1 CPU architecture BA1 = 201, /// Beyond BA2 CPU architecture BA2 = 202, /// XMOS xCORE processor family XCORE = 203, /// Microchip 8-bit PIC(r) family MCHP_PIC = 204, /// Reserved by Intel INTEL205 = 205, /// Reserved by Intel INTEL206 = 206, /// Reserved by Intel INTEL207 = 207, /// Reserved by Intel INTEL208 = 208, /// Reserved by Intel INTEL209 = 209, /// KM211 KM32 32-bit processor KM32 = 210, /// KM211 KMX32 32-bit processor KMX32 = 211, /// KM211 KMX16 16-bit processor KMX16 = 212, /// KM211 KMX8 8-bit processor KMX8 = 213, /// KM211 KVARC processor KVARC = 214, /// Paneve CDP architecture family CDP = 215, /// Cognitive Smart Memory Processor COGE = 216, /// iCelero CoolEngine COOL = 217, /// Nanoradio Optimized RISC NORC = 218, /// CSR Kalimba architecture family CSR_KALIMBA = 219, /// AMD GPU architecture AMDGPU = 224, /// RISC-V RISCV = 243, /// Lanai 32-bit processor LANAI = 244, /// Linux kernel bpf virtual machine BPF = 247, /// C-SKY CSKY = 252, /// Fujitsu FR-V FRV = 0x5441, _, pub fn toTargetCpuArch(em: EM) ?std.Target.Cpu.Arch { return switch (em) { .AVR => .avr, .MSP430 => .msp430, .ARC => .arc, .ARM => .arm, .HEXAGON => .hexagon, .@"68K" => .m68k, .MIPS => .mips, .MIPS_RS3_LE => .mipsel, .PPC => .powerpc, .SPARC => .sparc, .@"386" => .x86, .XCORE => .xcore, .CSR_KALIMBA => .kalimba, .LANAI => .lanai, .AARCH64 => .aarch64, .PPC64 => .powerpc64, .RISCV => .riscv64, .X86_64 => .x86_64, .BPF => .bpfel, .SPARCV9 => .sparc64, .S390 => .s390x, .SPU_2 => .spu_2, // there's many cases we don't (yet) handle, or will never have a // zig target cpu arch equivalent (such as null). else => null, }; } }; pub const GRP_COMDAT = 1; /// Section data should be writable during execution. pub const SHF_WRITE = 0x1; /// Section occupies memory during program execution. pub const SHF_ALLOC = 0x2; /// Section contains executable machine instructions. pub const SHF_EXECINSTR = 0x4; /// The data in this section may be merged. pub const SHF_MERGE = 0x10; /// The data in this section is null-terminated strings. pub const SHF_STRINGS = 0x20; /// A field in this section holds a section header table index. pub const SHF_INFO_LINK = 0x40; /// Adds special ordering requirements for link editors. pub const SHF_LINK_ORDER = 0x80; /// This section requires special OS-specific processing to avoid incorrect /// behavior. pub const SHF_OS_NONCONFORMING = 0x100; /// This section is a member of a section group. pub const SHF_GROUP = 0x200; /// This section holds Thread-Local Storage. pub const SHF_TLS = 0x400; /// Identifies a section containing compressed data. pub const SHF_COMPRESSED = 0x800; /// Not to be GCed by the linker pub const SHF_GNU_RETAIN = 0x200000; /// This section is excluded from the final executable or shared library. pub const SHF_EXCLUDE = 0x80000000; /// Start of target-specific flags. pub const SHF_MASKOS = 0x0ff00000; /// Bits indicating processor-specific flags. pub const SHF_MASKPROC = 0xf0000000; /// All sections with the "d" flag are grouped together by the linker to form /// the data section and the dp register is set to the start of the section by /// the boot code. pub const XCORE_SHF_DP_SECTION = 0x10000000; /// All sections with the "c" flag are grouped together by the linker to form /// the constant pool and the cp register is set to the start of the constant /// pool by the boot code. pub const XCORE_SHF_CP_SECTION = 0x20000000; /// If an object file section does not have this flag set, then it may not hold /// more than 2GB and can be freely referred to in objects using smaller code /// models. Otherwise, only objects using larger code models can refer to them. /// For example, a medium code model object can refer to data in a section that /// sets this flag besides being able to refer to data in a section that does /// not set it; likewise, a small code model object can refer only to code in a /// section that does not set this flag. pub const SHF_X86_64_LARGE = 0x10000000; /// All sections with the GPREL flag are grouped into a global data area /// for faster accesses pub const SHF_HEX_GPREL = 0x10000000; /// Section contains text/data which may be replicated in other sections. /// Linker must retain only one copy. pub const SHF_MIPS_NODUPES = 0x01000000; /// Linker must generate implicit hidden weak names. pub const SHF_MIPS_NAMES = 0x02000000; /// Section data local to process. pub const SHF_MIPS_LOCAL = 0x04000000; /// Do not strip this section. pub const SHF_MIPS_NOSTRIP = 0x08000000; /// Section must be part of global data area. pub const SHF_MIPS_GPREL = 0x10000000; /// This section should be merged. pub const SHF_MIPS_MERGE = 0x20000000; /// Address size to be inferred from section entry size. pub const SHF_MIPS_ADDR = 0x40000000; /// Section data is string data by default. pub const SHF_MIPS_STRING = 0x80000000; /// Make code section unreadable when in execute-only mode pub const SHF_ARM_PURECODE = 0x2000000; /// Execute pub const PF_X = 1; /// Write pub const PF_W = 2; /// Read pub const PF_R = 4; /// Bits for operating system-specific semantics. pub const PF_MASKOS = 0x0ff00000; /// Bits for processor-specific semantics. pub const PF_MASKPROC = 0xf0000000; /// Undefined section pub const SHN_UNDEF = 0; /// Start of reserved indices pub const SHN_LORESERVE = 0xff00; /// Start of processor-specific pub const SHN_LOPROC = 0xff00; /// End of processor-specific pub const SHN_HIPROC = 0xff1f; pub const SHN_LIVEPATCH = 0xff20; /// Associated symbol is absolute pub const SHN_ABS = 0xfff1; /// Associated symbol is common pub const SHN_COMMON = 0xfff2; /// End of reserved indices pub const SHN_HIRESERVE = 0xffff; // Legal values for ch_type (compression algorithm). pub const COMPRESS = enum(u32) { ZLIB = 1, ZSTD = 2, LOOS = 0x60000000, HIOS = 0x6fffffff, LOPROC = 0x70000000, HIPROC = 0x7fffffff, _, }; /// AMD x86-64 relocations. pub const R_X86_64 = enum(u32) { /// No reloc NONE = 0, /// Direct 64 bit @"64" = 1, /// PC relative 32 bit signed PC32 = 2, /// 32 bit GOT entry GOT32 = 3, /// 32 bit PLT address PLT32 = 4, /// Copy symbol at runtime COPY = 5, /// Create GOT entry GLOB_DAT = 6, /// Create PLT entry JUMP_SLOT = 7, /// Adjust by program base RELATIVE = 8, /// 32 bit signed PC relative offset to GOT GOTPCREL = 9, /// Direct 32 bit zero extended @"32" = 10, /// Direct 32 bit sign extended @"32S" = 11, /// Direct 16 bit zero extended @"16" = 12, /// 16 bit sign extended pc relative PC16 = 13, /// Direct 8 bit sign extended @"8" = 14, /// 8 bit sign extended pc relative PC8 = 15, /// ID of module containing symbol DTPMOD64 = 16, /// Offset in module's TLS block DTPOFF64 = 17, /// Offset in initial TLS block TPOFF64 = 18, /// 32 bit signed PC relative offset to two GOT entries for GD symbol TLSGD = 19, /// 32 bit signed PC relative offset to two GOT entries for LD symbol TLSLD = 20, /// Offset in TLS block DTPOFF32 = 21, /// 32 bit signed PC relative offset to GOT entry for IE symbol GOTTPOFF = 22, /// Offset in initial TLS block TPOFF32 = 23, /// PC relative 64 bit PC64 = 24, /// 64 bit offset to GOT GOTOFF64 = 25, /// 32 bit signed pc relative offset to GOT GOTPC32 = 26, /// 64 bit GOT entry offset GOT64 = 27, /// 64 bit PC relative offset to GOT entry GOTPCREL64 = 28, /// 64 bit PC relative offset to GOT GOTPC64 = 29, /// Like GOT64, says PLT entry needed GOTPLT64 = 30, /// 64-bit GOT relative offset to PLT entry PLTOFF64 = 31, /// Size of symbol plus 32-bit addend SIZE32 = 32, /// Size of symbol plus 64-bit addend SIZE64 = 33, /// GOT offset for TLS descriptor GOTPC32_TLSDESC = 34, /// Marker for call through TLS descriptor TLSDESC_CALL = 35, /// TLS descriptor TLSDESC = 36, /// Adjust indirectly by program base IRELATIVE = 37, /// 64-bit adjust by program base RELATIVE64 = 38, /// 39 Reserved was PC32_BND /// 40 Reserved was PLT32_BND /// Load from 32 bit signed pc relative offset to GOT entry without REX prefix, relaxable GOTPCRELX = 41, /// Load from 32 bit signed PC relative offset to GOT entry with REX prefix, relaxable REX_GOTPCRELX = 42, _, }; /// AArch64 relocs. pub const R_AARCH64 = enum(u32) { /// No relocation. NONE = 0, /// ILP32 AArch64 relocs. /// Direct 32 bit. P32_ABS32 = 1, /// Copy symbol at runtime. P32_COPY = 180, /// Create GOT entry. P32_GLOB_DAT = 181, /// Create PLT entry. P32_JUMP_SLOT = 182, /// Adjust by program base. P32_RELATIVE = 183, /// Module number, 32 bit. P32_TLS_DTPMOD = 184, /// Module-relative offset, 32 bit. P32_TLS_DTPREL = 185, /// TP-relative offset, 32 bit. P32_TLS_TPREL = 186, /// TLS Descriptor. P32_TLSDESC = 187, /// STT_GNU_IFUNC relocation. P32_IRELATIVE = 188, /// LP64 AArch64 relocs. /// Direct 64 bit. ABS64 = 257, /// Direct 32 bit. ABS32 = 258, /// Direct 16-bit. ABS16 = 259, /// PC-relative 64-bit. PREL64 = 260, /// PC-relative 32-bit. PREL32 = 261, /// PC-relative 16-bit. PREL16 = 262, /// Dir. MOVZ imm. from bits 15:0. MOVW_UABS_G0 = 263, /// Likewise for MOVK; no check. MOVW_UABS_G0_NC = 264, /// Dir. MOVZ imm. from bits 31:16. MOVW_UABS_G1 = 265, /// Likewise for MOVK; no check. MOVW_UABS_G1_NC = 266, /// Dir. MOVZ imm. from bits 47:32. MOVW_UABS_G2 = 267, /// Likewise for MOVK; no check. MOVW_UABS_G2_NC = 268, /// Dir. MOV{K,Z} imm. from 63:48. MOVW_UABS_G3 = 269, /// Dir. MOV{N,Z} imm. from 15:0. MOVW_SABS_G0 = 270, /// Dir. MOV{N,Z} imm. from 31:16. MOVW_SABS_G1 = 271, /// Dir. MOV{N,Z} imm. from 47:32. MOVW_SABS_G2 = 272, /// PC-rel. LD imm. from bits 20:2. LD_PREL_LO19 = 273, /// PC-rel. ADR imm. from bits 20:0. ADR_PREL_LO21 = 274, /// Page-rel. ADRP imm. from 32:12. ADR_PREL_PG_HI21 = 275, /// Likewise; no overflow check. ADR_PREL_PG_HI21_NC = 276, /// Dir. ADD imm. from bits 11:0. ADD_ABS_LO12_NC = 277, /// Likewise for LD/ST; no check. LDST8_ABS_LO12_NC = 278, /// PC-rel. TBZ/TBNZ imm. from 15:2. TSTBR14 = 279, /// PC-rel. cond. br. imm. from 20:2. CONDBR19 = 280, /// PC-rel. B imm. from bits 27:2. JUMP26 = 282, /// Likewise for CALL. CALL26 = 283, /// Dir. ADD imm. from bits 11:1. LDST16_ABS_LO12_NC = 284, /// Likewise for bits 11:2. LDST32_ABS_LO12_NC = 285, /// Likewise for bits 11:3. LDST64_ABS_LO12_NC = 286, /// PC-rel. MOV{N,Z} imm. from 15:0. MOVW_PREL_G0 = 287, /// Likewise for MOVK; no check. MOVW_PREL_G0_NC = 288, /// PC-rel. MOV{N,Z} imm. from 31:16. MOVW_PREL_G1 = 289, /// Likewise for MOVK; no check. MOVW_PREL_G1_NC = 290, /// PC-rel. MOV{N,Z} imm. from 47:32. MOVW_PREL_G2 = 291, /// Likewise for MOVK; no check. MOVW_PREL_G2_NC = 292, /// PC-rel. MOV{N,Z} imm. from 63:48. MOVW_PREL_G3 = 293, /// Dir. ADD imm. from bits 11:4. LDST128_ABS_LO12_NC = 299, /// GOT-rel. off. MOV{N,Z} imm. 15:0. MOVW_GOTOFF_G0 = 300, /// Likewise for MOVK; no check. MOVW_GOTOFF_G0_NC = 301, /// GOT-rel. o. MOV{N,Z} imm. 31:16. MOVW_GOTOFF_G1 = 302, /// Likewise for MOVK; no check. MOVW_GOTOFF_G1_NC = 303, /// GOT-rel. o. MOV{N,Z} imm. 47:32. MOVW_GOTOFF_G2 = 304, /// Likewise for MOVK; no check. MOVW_GOTOFF_G2_NC = 305, /// GOT-rel. o. MOV{N,Z} imm. 63:48. MOVW_GOTOFF_G3 = 306, /// GOT-relative 64-bit. GOTREL64 = 307, /// GOT-relative 32-bit. GOTREL32 = 308, /// PC-rel. GOT off. load imm. 20:2. GOT_LD_PREL19 = 309, /// GOT-rel. off. LD/ST imm. 14:3. LD64_GOTOFF_LO15 = 310, /// P-page-rel. GOT off. ADRP 32:12. ADR_GOT_PAGE = 311, /// Dir. GOT off. LD/ST imm. 11:3. LD64_GOT_LO12_NC = 312, /// GOT-page-rel. GOT off. LD/ST 14:3 LD64_GOTPAGE_LO15 = 313, /// PC-relative ADR imm. 20:0. TLSGD_ADR_PREL21 = 512, /// page-rel. ADRP imm. 32:12. TLSGD_ADR_PAGE21 = 513, /// direct ADD imm. from 11:0. TLSGD_ADD_LO12_NC = 514, /// GOT-rel. MOV{N,Z} 31:16. TLSGD_MOVW_G1 = 515, /// GOT-rel. MOVK imm. 15:0. TLSGD_MOVW_G0_NC = 516, /// Like 512; local dynamic model. TLSLD_ADR_PREL21 = 517, /// Like 513; local dynamic model. TLSLD_ADR_PAGE21 = 518, /// Like 514; local dynamic model. TLSLD_ADD_LO12_NC = 519, /// Like 515; local dynamic model. TLSLD_MOVW_G1 = 520, /// Like 516; local dynamic model. TLSLD_MOVW_G0_NC = 521, /// TLS PC-rel. load imm. 20:2. TLSLD_LD_PREL19 = 522, /// TLS DTP-rel. MOV{N,Z} 47:32. TLSLD_MOVW_DTPREL_G2 = 523, /// TLS DTP-rel. MOV{N,Z} 31:16. TLSLD_MOVW_DTPREL_G1 = 524, /// Likewise; MOVK; no check. TLSLD_MOVW_DTPREL_G1_NC = 525, /// TLS DTP-rel. MOV{N,Z} 15:0. TLSLD_MOVW_DTPREL_G0 = 526, /// Likewise; MOVK; no check. TLSLD_MOVW_DTPREL_G0_NC = 527, /// DTP-rel. ADD imm. from 23:12. TLSLD_ADD_DTPREL_HI12 = 528, /// DTP-rel. ADD imm. from 11:0. TLSLD_ADD_DTPREL_LO12 = 529, /// Likewise; no ovfl. check. TLSLD_ADD_DTPREL_LO12_NC = 530, /// DTP-rel. LD/ST imm. 11:0. TLSLD_LDST8_DTPREL_LO12 = 531, /// Likewise; no check. TLSLD_LDST8_DTPREL_LO12_NC = 532, /// DTP-rel. LD/ST imm. 11:1. TLSLD_LDST16_DTPREL_LO12 = 533, /// Likewise; no check. TLSLD_LDST16_DTPREL_LO12_NC = 534, /// DTP-rel. LD/ST imm. 11:2. TLSLD_LDST32_DTPREL_LO12 = 535, /// Likewise; no check. TLSLD_LDST32_DTPREL_LO12_NC = 536, /// DTP-rel. LD/ST imm. 11:3. TLSLD_LDST64_DTPREL_LO12 = 537, /// Likewise; no check. TLSLD_LDST64_DTPREL_LO12_NC = 538, /// GOT-rel. MOV{N,Z} 31:16. TLSIE_MOVW_GOTTPREL_G1 = 539, /// GOT-rel. MOVK 15:0. TLSIE_MOVW_GOTTPREL_G0_NC = 540, /// Page-rel. ADRP 32:12. TLSIE_ADR_GOTTPREL_PAGE21 = 541, /// Direct LD off. 11:3. TLSIE_LD64_GOTTPREL_LO12_NC = 542, /// PC-rel. load imm. 20:2. TLSIE_LD_GOTTPREL_PREL19 = 543, /// TLS TP-rel. MOV{N,Z} 47:32. TLSLE_MOVW_TPREL_G2 = 544, /// TLS TP-rel. MOV{N,Z} 31:16. TLSLE_MOVW_TPREL_G1 = 545, /// Likewise; MOVK; no check. TLSLE_MOVW_TPREL_G1_NC = 546, /// TLS TP-rel. MOV{N,Z} 15:0. TLSLE_MOVW_TPREL_G0 = 547, /// Likewise; MOVK; no check. TLSLE_MOVW_TPREL_G0_NC = 548, /// TP-rel. ADD imm. 23:12. TLSLE_ADD_TPREL_HI12 = 549, /// TP-rel. ADD imm. 11:0. TLSLE_ADD_TPREL_LO12 = 550, /// Likewise; no ovfl. check. TLSLE_ADD_TPREL_LO12_NC = 551, /// TP-rel. LD/ST off. 11:0. TLSLE_LDST8_TPREL_LO12 = 552, /// Likewise; no ovfl. check. TLSLE_LDST8_TPREL_LO12_NC = 553, /// TP-rel. LD/ST off. 11:1. TLSLE_LDST16_TPREL_LO12 = 554, /// Likewise; no check. TLSLE_LDST16_TPREL_LO12_NC = 555, /// TP-rel. LD/ST off. 11:2. TLSLE_LDST32_TPREL_LO12 = 556, /// Likewise; no check. TLSLE_LDST32_TPREL_LO12_NC = 557, /// TP-rel. LD/ST off. 11:3. TLSLE_LDST64_TPREL_LO12 = 558, /// Likewise; no check. TLSLE_LDST64_TPREL_LO12_NC = 559, /// PC-rel. load immediate 20:2. TLSDESC_LD_PREL19 = 560, /// PC-rel. ADR immediate 20:0. TLSDESC_ADR_PREL21 = 561, /// Page-rel. ADRP imm. 32:12. TLSDESC_ADR_PAGE21 = 562, /// Direct LD off. from 11:3. TLSDESC_LD64_LO12 = 563, /// Direct ADD imm. from 11:0. TLSDESC_ADD_LO12 = 564, /// GOT-rel. MOV{N,Z} imm. 31:16. TLSDESC_OFF_G1 = 565, /// GOT-rel. MOVK imm. 15:0; no ck. TLSDESC_OFF_G0_NC = 566, /// Relax LDR. TLSDESC_LDR = 567, /// Relax ADD. TLSDESC_ADD = 568, /// Relax BLR. TLSDESC_CALL = 569, /// TP-rel. LD/ST off. 11:4. TLSLE_LDST128_TPREL_LO12 = 570, /// Likewise; no check. TLSLE_LDST128_TPREL_LO12_NC = 571, /// DTP-rel. LD/ST imm. 11:4. TLSLD_LDST128_DTPREL_LO12 = 572, /// Likewise; no check. TLSLD_LDST128_DTPREL_LO12_NC = 573, /// Copy symbol at runtime. COPY = 1024, /// Create GOT entry. GLOB_DAT = 1025, /// Create PLT entry. JUMP_SLOT = 1026, /// Adjust by program base. RELATIVE = 1027, /// Module number, 64 bit. TLS_DTPMOD = 1028, /// Module-relative offset, 64 bit. TLS_DTPREL = 1029, /// TP-relative offset, 64 bit. TLS_TPREL = 1030, /// TLS Descriptor. TLSDESC = 1031, /// STT_GNU_IFUNC relocation. IRELATIVE = 1032, _, }; /// RISC-V relocations. pub const R_RISCV = enum(u32) { NONE = 0, @"32" = 1, @"64" = 2, RELATIVE = 3, COPY = 4, JUMP_SLOT = 5, TLS_DTPMOD32 = 6, TLS_DTPMOD64 = 7, TLS_DTPREL32 = 8, TLS_DTPREL64 = 9, TLS_TPREL32 = 10, TLS_TPREL64 = 11, TLSDESC = 12, BRANCH = 16, JAL = 17, CALL = 18, CALL_PLT = 19, GOT_HI20 = 20, TLS_GOT_HI20 = 21, TLS_GD_HI20 = 22, PCREL_HI20 = 23, PCREL_LO12_I = 24, PCREL_LO12_S = 25, HI20 = 26, LO12_I = 27, LO12_S = 28, TPREL_HI20 = 29, TPREL_LO12_I = 30, TPREL_LO12_S = 31, TPREL_ADD = 32, ADD8 = 33, ADD16 = 34, ADD32 = 35, ADD64 = 36, SUB8 = 37, SUB16 = 38, SUB32 = 39, SUB64 = 40, GNU_VTINHERIT = 41, GNU_VTENTRY = 42, ALIGN = 43, RVC_BRANCH = 44, RVC_JUMP = 45, RVC_LUI = 46, GPREL_I = 47, GPREL_S = 48, TPREL_I = 49, TPREL_S = 50, RELAX = 51, SUB6 = 52, SET6 = 53, SET8 = 54, SET16 = 55, SET32 = 56, @"32_PCREL" = 57, IRELATIVE = 58, PLT32 = 59, SET_ULEB128 = 60, SUB_ULEB128 = 61, _, }; pub const STV = enum(u2) { DEFAULT = 0, INTERNAL = 1, HIDDEN = 2, PROTECTED = 3, }; pub const ar_hdr = extern struct { /// Member file name, sometimes / terminated. ar_name: [16]u8, /// File date, decimal seconds since Epoch. ar_date: [12]u8, /// User ID, in ASCII format. ar_uid: [6]u8, /// Group ID, in ASCII format. ar_gid: [6]u8, /// File mode, in ASCII octal. ar_mode: [8]u8, /// File size, in ASCII decimal. ar_size: [10]u8, /// Always contains ARFMAG. ar_fmag: [2]u8, pub fn date(self: ar_hdr) std.fmt.ParseIntError!u64 { const value = mem.trimRight(u8, &self.ar_date, &[_]u8{0x20}); return std.fmt.parseInt(u64, value, 10); } pub fn size(self: ar_hdr) std.fmt.ParseIntError!u32 { const value = mem.trimRight(u8, &self.ar_size, &[_]u8{0x20}); return std.fmt.parseInt(u32, value, 10); } pub fn isStrtab(self: ar_hdr) bool { return mem.eql(u8, &self.ar_name, STRNAME); } pub fn isSymtab(self: ar_hdr) bool { return mem.eql(u8, &self.ar_name, SYMNAME); } pub fn isSymtab64(self: ar_hdr) bool { return mem.eql(u8, &self.ar_name, SYM64NAME); } pub fn isSymdef(self: ar_hdr) bool { return mem.eql(u8, &self.ar_name, SYMDEFNAME); } pub fn isSymdefSorted(self: ar_hdr) bool { return mem.eql(u8, &self.ar_name, SYMDEFSORTEDNAME); } pub fn name(self: *const ar_hdr) ?[]const u8 { const value = &self.ar_name; if (value[0] == '/') return null; const sentinel = mem.indexOfScalar(u8, value, '/') orelse value.len; return value[0..sentinel]; } pub fn nameOffset(self: ar_hdr) std.fmt.ParseIntError!?u32 { const value = &self.ar_name; if (value[0] != '/') return null; const trimmed = mem.trimRight(u8, value, &[_]u8{0x20}); return try std.fmt.parseInt(u32, trimmed[1..], 10); } }; fn genSpecialMemberName(comptime name: []const u8) *const [16]u8 { assert(name.len <= 16); const padding = 16 - name.len; return name ++ &[_]u8{0x20} ** padding; } // Archive files start with the ARMAG identifying string. Then follows a // `struct ar_hdr', and as many bytes of member file data as its `ar_size' // member indicates, for each member file. /// String that begins an archive file. pub const ARMAG = "!<arch>\n"; /// String in ar_fmag at the end of each header. pub const ARFMAG = "`\n"; /// 32-bit symtab identifier pub const SYMNAME = genSpecialMemberName("/"); /// Strtab identifier pub const STRNAME = genSpecialMemberName("//"); /// 64-bit symtab identifier pub const SYM64NAME = genSpecialMemberName("/SYM64/"); pub const SYMDEFNAME = genSpecialMemberName("__.SYMDEF"); pub const SYMDEFSORTEDNAME = genSpecialMemberName("__.SYMDEF SORTED"); |
Generated by zstd-live on 2025-08-12 12:37:58 UTC. |